On Tue, Jul 14, 2020 at 11:35 AM LIU Zhiwei <zhiwei_...@c-sky.com> wrote:
> > > On 2020/7/14 10:59, Frank Chang wrote: > > On Sat, Jul 11, 2020 at 12:27 AM Richard Henderson < > richard.hender...@linaro.org> wrote: > >> On 7/10/20 3:48 AM, frank.ch...@sifive.com wrote: >> > From: Frank Chang <frank.ch...@sifive.com> >> > >> > vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the >> > shift immediate value to be within the range: [0.. SEW bits]. >> > Otherwise, it will hit the assertion: >> > tcg_debug_assert(shift >= 0 && shift < (8 << vece)); >> > >> > However, RVV spec does not have such constraint, therefore we have to >> > use helper functions instead. >> >> Why do you say that? It does have such a constraint: >> >> # Only the low lg2(SEW) bits are read to obtain the shift amount from a >> register value. >> >> While that only talks about the register value, I sincerely doubt that >> the same >> truncation does not actually apply to immediates. >> >> And if the entire immediate value does apply, the manual should certainly >> specify what should happen in that case. And at present it doesn't. >> >> It seems to me the bug is the bare use of GEN_OPIVI_GVEC_TRANS and thence >> do_opivi_gvec. The ZX parameter should be extended to more than just >> "zero vs >> sign-extend", it should have an option for truncating the immediate to >> s->sew. >> >> >> r~ >> > > The latest spec specified: > > Only the low *lg2(SEW) bits* are read to obtain the shift amount from a > *register > value*. > The *immediate* is treated as an *unsigned shift amount*, with a *maximum > shift amount of 31*. > > Looks like the shift amount in the immediate value is not relevant with > SEW setting. > If so, is it better to just use do_opivi_gvec() and implement the logic by > our own rather than using gvec IR? > > > In my opinion, it doesn't matter to truncate the immediate to s->sew > before calling the gvec IR, > whether the constraint of immediate exits or not. > > Zhiwei > > > Frank Chang > > > The current issue I've encountered is the test like: *vsetvli t0,t0,e8,m1,tu,mu,d1* *vsll.vi <http://vsll.vi> v30, v30, 27* where the SEW is 8 (i.e. vece = 0), but the immediate value is: 27. The instruction doesn't violate the requirement specified in spec as its value is less then 31. However, it can't pass *tcg_debug_assert(shift >= 0 && shift < (8 << vece));* assertion if tcg debug option is enabled. Frank Chang
