陳韋任 wrote:
> > As x86 doesn't use or need barrier instructions, when translating x86
> > to (say) run on ARM host, multi-threaded code that needs barriers
> > isn't easy to detect, so barriers may be required between every memory
> > access in the generated ARM code.
>
> Sounds awful to me. Rega
> As x86 doesn't use or need barrier instructions, when translating x86
> to (say) run on ARM host, multi-threaded code that needs barriers
> isn't easy to detect, so barriers may be required between every memory
> access in the generated ARM code.
Sounds awful to me. Regardless current QEMU's s
Hi,
I have modified QEMU to act as a TCG compiler and give me the TCG code for
the whole binary. However, I cannot find a way to obtain the last address
in the binary. The symbol table loaded into syminfos contains only the
address of the last symbol. Not the address of the last machine
instructio
陳韋任 wrote:
> What's load/store exclusive implementation?
It's how some architectures do atomic operations, instead of having
atomic instructions like x86 does.
> And as a general emulator, QEMU shouldn't implement any
> architecture-specific memory model, right? What comes into my mind
> is QEM
Peter Maydell wrote:
> > "guest binaries don't actually rely that much on the memory model."
> >
> > I think the reason is those guest binaries are single thread. Memory model
> > is
> > important in multi-threaded case. BTW, our binary translator now can
> > translate
> > x86 binary to ARM bina
On Fri, Jan 20, 2012 at 09:09:46AM +, Peter Maydell wrote:
> On 20 January 2012 06:12, 陳韋任 wrote:
> > Out of curiosity. What's ARM memory model? From the Wikipedia [1], it seems
> > ARMv7 has the same memory model as IA64.
>
> The ARM memory model is the set of semantics for memory
> accesse
> > I was not talking about semantics of individual instructions but semantics
> > of the whole multi-threaded program. Multi-threaded programs can lead to
> > several different (most of which are unintended) states of the CPU. What
> > states are possible is described in a mathematically rigorous
> I was not talking about semantics of individual instructions but semantics
> of the whole multi-threaded program. Multi-threaded programs can lead to
> several different (most of which are unintended) states of the CPU. What
> states are possible is described in a mathematically rigorous definiti
On 20 January 2012 09:44, 陳韋任 wrote:
> On Fri, Jan 20, 2012 at 09:09:46AM +, Peter Maydell wrote:
> AFAIK, LLVM defines it's own memory model [1] which is inspired by the C++11
> memory model. That's why I think instead of implementing architecture-specific
> memory model, QEMU should define
On 20 January 2012 06:12, 陳韋任 wrote:
> Out of curiosity. What's ARM memory model? From the Wikipedia [1], it seems
> ARMv7 has the same memory model as IA64.
The ARM memory model is the set of semantics for memory
accesses as defined in the ARM Architecture Reference
Manual (covering not just re
On 19 January 2012 16:00, Rajat Goyal wrote:
> Thank you so much for your help Peter. I was using version 0.15.1. On 1.0,
> it works like a dream!
Good.
> I was not talking about semantics of individual instructions but semantics
> of the whole multi-threaded program. Multi-threaded programs can
Thank you so much for your help Peter. I was using version 0.15.1. On 1.0,
it works like a dream!
I was not talking about semantics of individual instructions but semantics
of the whole multi-threaded program. Multi-threaded programs can lead to
several different (most of which are unintended) sta
On 17 January 2012 01:04, 陳韋任 wrote:
>> > What is the way out of this? The reason I need TCG code is because my
>> > project work is to write a semantics for TCG micro-operations and then
>> > compare my semantics with a semantics for ARM instructions being written by
>> > someone else. To test my
> > What is the way out of this? The reason I need TCG code is because my
> > project work is to write a semantics for TCG micro-operations and then
> > compare my semantics with a semantics for ARM instructions being written by
> > someone else. To test my semantics, I need the corresponding TCG c
On 16 January 2012 12:23, Rajat Goyal wrote:
> The situation is like this. The most basic multi-threaded program (using
> pthreads) which just prints something like "I am Thread 1" and "I am Thread
> 2" does not work over the QEMU user emulator. There are no output messages
> saying "I am thread 1
Thanks for your text, Stefan.
The situation is like this. The most basic multi-threaded program (using
pthreads) which just prints something like "I am Thread 1" and "I am Thread
2" does not work over the QEMU user emulator. There are no output messages
saying "I am thread 1" etc. when the program
On Sun, Jan 15, 2012 at 11:09:18PM +, Rajat Goyal wrote:
> I am doing a project to build a daemonic ARM emulator using QEMU. One of
> the requirements is to get the complete TCG code for any multi-threaded ARM
> program that I run on QEMU. I do not need QEMU to execute the program and
> show me
Hi
On Mon, Jan 16, 2012 at 06:09, Rajat Goyal wrote:
Is there a way by which I can get the
> complete TCG code for pthread parallel binaries in exchange for not making
> QEMU execute the binary?
The thing is, the way I see it, TCG is meant to be like JIT compiler.
Whereas what you're going t
I am doing a project to build a daemonic ARM emulator using QEMU. One of
the requirements is to get the complete TCG code for any multi-threaded ARM
program that I run on QEMU. I do not need QEMU to execute the program and
show me the output. Just the entire TCG code. The latest version of
qemu-arm
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