> I was not talking about semantics of individual instructions but semantics > of the whole multi-threaded program. Multi-threaded programs can lead to > several different (most of which are unintended) states of the CPU. What > states are possible is described in a mathematically rigorous definition of > the ARM memory model. My task is to implement this memory model over TCG > ops and then compare the results on several different (multi-threaded) > litmus tests with the implementation of the memory model over ARM > instructions. For the same task, I need QEMU to give me the TCG translation > for code which it never branches into and hence, never needs to translate > and execute (because ARM multiprocessors can perform speculative execution).
Out of curiosity. What's ARM memory model? From the Wikipedia [1], it seems ARMv7 has the same memory model as IA64. Regards, chenwj [1] http://en.wikipedia.org/wiki/Memory_ordering -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667 Homepage: http://people.cs.nctu.edu.tw/~chenwj
