陳韋任 wrote: > What's load/store exclusive implementation? It's how some architectures do atomic operations, instead of having atomic instructions like x86 does.
> And as a general emulator, QEMU shouldn't implement any > architecture-specific memory model, right? What comes into my mind > is QEMU only need to follow guest memory operations when translates > guest binary to TCG ops. When translate TCG ops to host binary, it > also has to be careful not to mess up the memory ordering. The error occurs when emulating two or more guest CPUs in parallel using two or more host CPUs for speed. Then "not mess up the memory ordering" may require barrier instructions in the host binary code, depending on the guest and host architectures. Without barrier instructions, the CPUs reorder memory accesses even if the instruction order is kept the same. This reordering done by the CPU is called the memory model. TCG cannot currently produce these barrier instructions, and it's not clear if it will ever be able to do so efficiently. -- Jamie
