On 12/02/2017 03:28 PM, Benjamin Herrenschmidt wrote:
> On Wed, 2017-11-29 at 17:23 +0100, Cédric Le Goater wrote:
>> On 11/29/2017 02:56 PM, Cédric Le Goater wrote:
>>> +switch (offset) {
>>> +case 0:
>>> +spapr_xive_source_eoi(xive, lisn);
>>
>> Hrm. I don't l
On Thu, 2017-11-30 at 15:28 +1100, David Gibson wrote:
>
> How does this work at the hardware level? Presumbly the actual
> hardware components don't communicate with the XIVE to request edge or
> level. So how does it know? Specific ranges for LSIs? If that we
> should probably do the same.
On Wed, 2017-11-29 at 17:23 +0100, Cédric Le Goater wrote:
> On 11/29/2017 02:56 PM, Cédric Le Goater wrote:
> > > > > > +switch (offset) {
> > > > > > +case 0:
> > > > > > +spapr_xive_source_eoi(xive, lisn);
> > > > >
> > > > > Hrm. I don't love that you're dealing with clearing
On Tue, 2017-11-28 at 17:38 +1100, David Gibson wrote:
> Hrm. I don't love that you're dealing with clearing that LSI bit
> here, but setting it at a different level.
>
> The state machines are doing my head in a bit, is there any way
> you could derive the STATUS_SENT bit from the PQ bits?
Yeah
On 11/30/2017 04:28 AM, David Gibson wrote:
> On Wed, Nov 29, 2017 at 05:23:25PM +0100, Cédric Le Goater wrote:
>> On 11/29/2017 02:56 PM, Cédric Le Goater wrote:
>>> +switch (offset) {
>>> +case 0:
>>> +spapr_xive_source_eoi(xive, lisn);
>>
>> Hrm. I don't love
On 11/30/2017 04:26 AM, David Gibson wrote:
> On Wed, Nov 29, 2017 at 02:56:39PM +0100, Cédric Le Goater wrote:
>> +switch (offset) {
>> +case 0:
>> +spapr_xive_source_eoi(xive, lisn);
>
> Hrm. I don't love that you're dealing with clearing that LSI bit
> he
On Wed, Nov 29, 2017 at 05:23:25PM +0100, Cédric Le Goater wrote:
> On 11/29/2017 02:56 PM, Cédric Le Goater wrote:
> > +switch (offset) {
> > +case 0:
> > +spapr_xive_source_eoi(xive, lisn);
>
> Hrm. I don't love that you're dealing with clearing that LSI bit
On Wed, Nov 29, 2017 at 02:56:39PM +0100, Cédric Le Goater wrote:
> +switch (offset) {
> +case 0:
> +spapr_xive_source_eoi(xive, lisn);
> >>>
> >>> Hrm. I don't love that you're dealing with clearing that LSI bit
> >>> here, but setting it at a different level.
> >>>
On 11/29/2017 02:56 PM, Cédric Le Goater wrote:
> +switch (offset) {
> +case 0:
> +spapr_xive_source_eoi(xive, lisn);
Hrm. I don't love that you're dealing with clearing that LSI bit
here, but setting it at a different level.
The state machines
+switch (offset) {
+case 0:
+spapr_xive_source_eoi(xive, lisn);
>>>
>>> Hrm. I don't love that you're dealing with clearing that LSI bit
>>> here, but setting it at a different level.
>>>
>>> The state machines are doing my head in a bit, is there any way
>>> you cou
On Tue, Nov 28, 2017 at 06:33:06PM +, Cédric Le Goater wrote:
> On 11/28/2017 06:38 AM, David Gibson wrote:
> > On Thu, Nov 23, 2017 at 02:29:40PM +0100, Cédric Le Goater wrote:
> >> Each interrupt source is associated with a two bit state machine
> >> called an Event State Buffer (ESB). The bi
On 11/28/2017 06:38 AM, David Gibson wrote:
> On Thu, Nov 23, 2017 at 02:29:40PM +0100, Cédric Le Goater wrote:
>> Each interrupt source is associated with a two bit state machine
>> called an Event State Buffer (ESB). The bits are named "P" (pending)
>> and "Q" (queued) and can be controlled by MM
On Thu, Nov 23, 2017 at 02:29:40PM +0100, Cédric Le Goater wrote:
> Each interrupt source is associated with a two bit state machine
> called an Event State Buffer (ESB). The bits are named "P" (pending)
> and "Q" (queued) and can be controlled by MMIO. It is used to trigger
> events. See code for
Each interrupt source is associated with a two bit state machine
called an Event State Buffer (ESB). The bits are named "P" (pending)
and "Q" (queued) and can be controlled by MMIO. It is used to trigger
events. See code for more details on the states and transitions.
The MMIO space for the ESB tr
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