On Thu, 2017-11-30 at 15:28 +1100, David Gibson wrote: > > How does this work at the hardware level? Presumbly the actual > hardware components don't communicate with the XIVE to request edge or > level. So how does it know? Specific ranges for LSIs? If that we > should probably do the same.
So the source controller and the IVE are separate. The source controller sends an internal MMIO to the IVE for "translating" the event into a queue etc... The IVE only see "events" which are effectively state transitions of the P bit of the source. The LSI vs MSI difference is thus entirely a property of the source HW. All the XIVE "Generic" built-in sources (the ones you can trigger with an MMIO, which we use in KVM for all the IPIs and virtual interrupts) are MSIs. You find 2 kind of blocks of LSIs in the chip, the one PSI block which has a handful or two of LSI sources for random "stuff" (LPC interrupt(s), i2c interrupts etc..) and the LSI blocks which are in each PHB. So the PHB has basically two different bits of logic, one for LSIs and one for MSIs. Their HW state machine is different. In fact in the PHB and the PSI, I think, there's even an MMIO backdoor register that allows you to see the "state" of the LSI (asserted). Cheers, Ben.
