On 11/30/2017 04:26 AM, David Gibson wrote:
> On Wed, Nov 29, 2017 at 02:56:39PM +0100, Cédric Le Goater wrote:
>>>>>> + switch (offset) {
>>>>>> + case 0:
>>>>>> + spapr_xive_source_eoi(xive, lisn);
>>>>>
>>>>> Hrm. I don't love that you're dealing with clearing that LSI bit
>>>>> here, but setting it at a different level.
>>>>>
>>>>> The state machines are doing my head in a bit, is there any way
>>>>> you could derive the STATUS_SENT bit from the PQ bits?
>>>>
>>>> Yes. I should.
>>>>
>>>> I am also lacking a guest driver to exercise these LSIs so I didn't
>>>> pay a lot of attention to level interrupts. Any idea ?
>>>
>>> How about an old-school emulated PCI device? Maybe rtl8139?
>>
>> Perfect. The current model is working but I will see how I can
>> improve it to use the PQ bits instead.
>>
>> I also found a couple of issues on the way.
>>
>> We do need the "#interrupt-cells" and "interrupt-controller"
>> properties. They are missing from the XIVE sPAPR specs but there
>> is no other way to find the parent controller for the LSIs ...
>> I have re-asked the pHyp team to include them in the specs and
>> fixed the QEMU model.
>
> Told ya so :).
I believed you ! I just needed a test case :)
C.
