On 28 February 2014 13:41, Rob Herring wrote:
> On Fri, Feb 28, 2014 at 4:41 AM, Peter Maydell
> wrote:
>> * for overrun, we should set the rsr bit in pl011_put_fifo
>>if the fifo is full; however, it looks from that function
>>as if we don't properly implement the documented behaviour
On Fri, Feb 28, 2014 at 4:41 AM, Peter Maydell wrote:
> On 28 February 2014 01:37, Rob Herring wrote:
>> From: Rob Herring
>>
>> Offset 4 is UARTRSR/UARTECR, not the UARTCR. As framing and parity errors
>> will never occur, we can ignore writes to this register.
>
> It's true that we'll never ge
On 28 February 2014 01:37, Rob Herring wrote:
> From: Rob Herring
>
> Offset 4 is UARTRSR/UARTECR, not the UARTCR. As framing and parity errors
> will never occur, we can ignore writes to this register.
It's true that we'll never get framing or parity errors,
but we can get break (and we ought t
From: Rob Herring
Offset 4 is UARTRSR/UARTECR, not the UARTCR. As framing and parity errors
will never occur, we can ignore writes to this register.
Signed-off-by: Rob Herring
---
hw/char/pl011.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/
