On 28 February 2014 13:41, Rob Herring <rob.herr...@linaro.org> wrote: > On Fri, Feb 28, 2014 at 4:41 AM, Peter Maydell <peter.mayd...@linaro.org> > wrote: >> * for overrun, we should set the rsr bit in pl011_put_fifo >> if the fifo is full; however, it looks from that function >> as if we don't properly implement the documented behaviour >> for a full fifo (s2.4.3 "UART operation" of the PL011 TRM >> is a pretty clear description) so I'd be OK with just adding >> a comment to pl011_put_fifo(): >> /* FIXME: FIFO overrun handling of excess data and setting >> * overrun status bits is not correctly implemented: >> * see PL011 TRM s2.4.3 "UART operation". >> */ >> (Of course if you want to implement overrun properly >> feel free ;-)) > > I don't think we can get an overrun. pl011_can_receive should prevent > ever getting a 17th character. If we allowed that, then we would get > overruns all the time. Effectively there is flow-control between qemu > and the pl011 model since there is no baudrate to limit the receive > speed.
Yes, you're right; I agree there's no point modelling overrun. thanks -- PMM
