Hi,
That's great, thank you! Looking forward to see the patch in the master branch!
Cheers,
bzt
On 3/12/19, Peter Maydell wrote:
> On Sun, 10 Mar 2019 at 11:02, bzt wrote:
>>
>> Hi,
>>
>> Okay, as you wish. My code works either way and on real hardware as
>> well, because I acknowledge the per
On Sun, 10 Mar 2019 at 11:02, bzt wrote:
>
> Hi,
>
> Okay, as you wish. My code works either way and on real hardware as
> well, because I acknowledge the periodic IRQ as soon as possible, so
> good for me.
Thanks; I'll get this version of the patch into git master
at some point in the next week.
Hi,
Okay, as you wish. My code works either way and on real hardware as
well, because I acknowledge the periodic IRQ as soon as possible, so
good for me.
Sign-off-by: Zoltán Baldaszti
Subject: [PATCH] Added periodic IRQ support for bcm2836_control local timer
diff --git a/hw/intc/bcm2836_control
On Sat, 9 Mar 2019 at 01:03, bzt wrote:
> Thanks for your answers. If I don't clear the INTENABLE flag, then the
> IRQ would keep firing constantly. This is not how the real hardware
> works: it triggers the IRQ once, and then it inhibits. The timer won't
> trigger the IRQ again until you acknowle
Hi,
Thanks for your answers. If I don't clear the INTENABLE flag, then the
IRQ would keep firing constantly. This is not how the real hardware
works: it triggers the IRQ once, and then it inhibits. The timer won't
trigger the IRQ again until you acknowledge it by writing the INTFLAG
into the ack r
On Thu, 7 Mar 2019 at 15:57, bzt wrote:
>
> Nope. I meant the second patch, sent on 4th Mar, which had all the
> things fixed you listed in your review.
>
> But here's the modification for your latest query. This one controls
> the timer depending on ENABLE bit. It sets the INTFLAG even if
> INTEN
On Thu, 7 Mar 2019 at 15:27, bzt wrote:
> Yes, could be. The QA7 spec is not really detailed, and calling both
> timers simply ARM timers can be misleading. But it's not relevant
> anyway from the IRQ's point of view. My latest patch checks both bits
> to be set to generate the IRQ, so it does not
Nope. I meant the second patch, sent on 4th Mar, which had all the
things fixed you listed in your review.
But here's the modification for your latest query. This one controls
the timer depending on ENABLE bit. It sets the INTFLAG even if
INTENABLE is not set, and only raises the IRQ if both are s
Hi,
Yes, could be. The QA7 spec is not really detailed, and calling both
timers simply ARM timers can be misleading. But it's not relevant
anyway from the IRQ's point of view. My latest patch checks both bits
to be set to generate the IRQ, so it does not really matter. As I've
said, this patch add
On Mon, 4 Mar 2019 at 19:27, bzt wrote:
>
> On 3/4/19, Peter Maydell wrote:
> >> + * The IRQ_TIMER support is still very basic, does not handle timer
> >> access,
> >> + * and such there's no point in enabling it without the interrupt flag
> >> set.
> >
> > Can you be more precise about what's mi
Hi Peter,
Here's the modified patch. I've changed the comment, I hope now it
makes clear that dispite this patch handles the timer enable bit
(which is required for the interrupt), it only adds the periodic IRQ
feature, and not the full timer functionality.
Otherwise I've modified everything you
Hi,
Thanks for the review! Most of it makes sense, and I'll modify the
patch accordingly. There are few things though, mostly related to
emulating this unique timer.
On 3/4/19, Peter Maydell wrote:
> OK, here are my substantive review comments.
>
>> diff --git a/hw/intc/bcm2836_control.c b/hw/in
On Tue, 26 Feb 2019 at 11:38, bzt wrote:
>
> Dear qemu developers,
>
> Honestly SubmitAPatch is a bit complicated for me, so I'm hoping I've
> done everything right. To be sure, you can find my patch here:
> https://github.com/bztsrc/qemu-local-timer and diff against the latest
> github repo here:
Hi Andrew,
That's great news, I'll then bring those drivers up to the modern qemu API!
Maybe that's a Linux kernel module configuration issue as well, but
with the BCM System Timer small delays depend on polling the counter.
Without the qemu support that counter register remains zero, causing
an
> From: bzt
> Sent: Wednesday, 27 February 2019 03:54
>
> I'd like to add more drivers for the bcm283[567] too, and this question goes
> to
> Andrew Baumann mostly. I've seen implemented those missing drivers in his
> repo, which aren't in the qemu mainline yet. I don't want to reinvent the
> w
Hi Peter,
Thank you very much! Let me know if I need to modify anything! Btw you
should update the maintainer's list, currently it does not list you as
a reviewer :-)
I'd like to add more drivers for the bcm283[567] too, and this
question goes to Andrew Baumann mostly. I've seen implemented those
On Tue, 26 Feb 2019 at 11:38, bzt wrote:
>
> Dear qemu developers,
>
> Honestly SubmitAPatch is a bit complicated for me, so I'm hoping I've
> done everything right. To be sure, you can find my patch here:
> https://github.com/bztsrc/qemu-local-timer and diff against the latest
> github repo here:
Dear qemu developers,
Honestly SubmitAPatch is a bit complicated for me, so I'm hoping I've
done everything right. To be sure, you can find my patch here:
https://github.com/bztsrc/qemu-local-timer and diff against the latest
github repo here:
https://github.com/bztsrc/qemu-local-timer/blob/patche
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