Hi, That's great, thank you! Looking forward to see the patch in the master branch!
Cheers, bzt On 3/12/19, Peter Maydell <peter.mayd...@linaro.org> wrote: > On Sun, 10 Mar 2019 at 11:02, bzt <bztem...@gmail.com> wrote: >> >> Hi, >> >> Okay, as you wish. My code works either way and on real hardware as >> well, because I acknowledge the periodic IRQ as soon as possible, so >> good for me. > > Thanks; I'll get this version of the patch into git master > at some point in the next week. > > (I happened to have an rpi2 to hand, so I wrote a little test > program to check what the behaviour of the h/w is, and it does > indeed not clear the INTEN bit when it signals an IRQ, > and it doesn't clear the IRQ line until the guest clears the > interrupt flag: so if your IRQ handler doesn't clear the flag > by writing to the register then the IRQ will 'scream' (fire > continually) both on QEMU and on the real hardware. So I think > the data sheet is correct here, though it certainly has its share > of errors...) > > thanks > -- PMM >
