> On Oct 21, 2021, at 11:11 PM, Cédric Le Goater wrote:
>
>>> And the FMC registers are just an alias to write
>>> to these watchdog 2 registers?
>> If this is the same watchdog mapped into the FMC, I would say yes
>> and the logic generate load/stores transactions on the AHB bus.
>> Adding an
And the FMC registers are just an alias to write
to these watchdog 2 registers?
If this is the same watchdog mapped into the FMC, I would say yes
and the logic generate load/stores transactions on the AHB bus.
Adding an address space for the WDT registers in the model is the
closer we can get w
On 10/20/21 06:57, Peter Delevoryas wrote:
On Oct 18, 2021, at 6:26 AM, Cédric Le Goater wrote:
Hello,
The Aspeed SoCs have a dual boot function for firmware fail-over
recovery. The system auto-reboots from the second flash if the main
flash does not boot successfully within a certain amoun
> On Oct 18, 2021, at 6:26 AM, Cédric Le Goater wrote:
>
> Hello,
>
> The Aspeed SoCs have a dual boot function for firmware fail-over
> recovery. The system auto-reboots from the second flash if the main
> flash does not boot successfully within a certain amount of time. This
> function is ca
Hello,
The Aspeed SoCs have a dual boot function for firmware fail-over
recovery. The system auto-reboots from the second flash if the main
flash does not boot successfully within a certain amount of time. This
function is called alternate boot (ABR) in the FMC controllers.
On the AST2600, the AB
