Hello,
The Aspeed SoCs have a dual boot function for firmware fail-over
recovery. The system auto-reboots from the second flash if the main
flash does not boot successfully within a certain amount of time. This
function is called alternate boot (ABR) in the FMC controllers.
On the AST2600, the ABR registers controlling the 2nd watchdog timer
were moved from the watchdog register to the FMC controller. To
control WDT2 through the FMC model register set, this series creates a
local address space on top of WDT2 memory region.
To test on the fuji-bmc machine, run :
devmem 0x1e620064
devmem 0x1e78504C
devmem 0x1e620064 32 0xffffffff
devmem 0x1e620064
devmem 0x1e78504C
Thanks
C.
Changes since v2:
- introduce a container region for the WDT2 register address space
- introduce a container region for the flash mmio address space
Cédric Le Goater (5):
aspeed/wdt: Introduce a container for the MMIO region
aspeed: Initialize the watchdog device models before the FMC models
aspeed/smc: Improve support for the alternate boot function
aspeed/smc: Use a container for the flash mmio address space
speed/sdhci: Add trace events
include/hw/ssi/aspeed_smc.h | 5 +-
include/hw/watchdog/wdt_aspeed.h | 1 +
hw/arm/aspeed_ast2600.c | 38 +++++++-------
hw/arm/aspeed_soc.c | 36 ++++++-------
hw/sd/aspeed_sdhci.c | 5 ++
hw/ssi/aspeed_smc.c | 89 +++++++++++++++++++++++++++++---
hw/watchdog/wdt_aspeed.c | 6 ++-
hw/sd/trace-events | 4 ++
hw/ssi/trace-events | 1 +
9 files changed, 141 insertions(+), 44 deletions(-)
--
2.31.1
