[PATCH v2] hw/pci-host/gt64120.c: Fix PCI host bridge endianness handling

The GT-64120 PCI controller requires special handling where: 1. Host bridge (device 0) must use native endianness 2. Other devices follow MByteSwap bit in GT_PCI0_CMD Previous implementation accidentally swapped all accesses, breaking host bridge detection (lspci -d 11ab:4620). This patch: - Adds

Re: [PATCH v2] hw/pci-host/gt64120.c: Fix PCI host bridge endianness handling

On Sat, Mar 29, 2025 at 5:18 PM Philippe Mathieu-Daudé wrote: > Hi Rakesh, > > On 29/3/25 01:49, rakeshj wrote: > > The GT-64120 PCI controller requires special handling where: > > 1. Host bridge (device 0) must use native endianness > > 2. Other devices follow MByteSwap bit in GT_PCI0_CMD > > >

Re: [PATCH v2] hw/pci-host/gt64120.c: Fix PCI host bridge endianness handling

Thanks, BALATON I looked into PCI_BUS_NUM and PCI_SLOT from include/hw/pci/pci.h (L15-24): - PCI_BUS_NUM(x) (((x) >> 8) & 0xff)) --> bits 15-8. - PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)), which don’t align properly with the 32-bit phb->config_reg layout used in your GT-64120 . Since these macros ar

Re: [PATCH v2] hw/pci-host/gt64120.c: Fix PCI host bridge endianness handling

On Sat, 29 Mar 2025, Philippe Mathieu-Daudé wrote: Hi Rakesh, On 29/3/25 01:49, rakeshj wrote: The GT-64120 PCI controller requires special handling where: 1. Host bridge (device 0) must use native endianness 2. Other devices follow MByteSwap bit in GT_PCI0_CMD Previous implementation accident

Re: [PATCH v2] hw/pci-host/gt64120.c: Fix PCI host bridge endianness handling

Hi Rakesh, On 29/3/25 01:49, rakeshj wrote: The GT-64120 PCI controller requires special handling where: 1. Host bridge (device 0) must use native endianness 2. Other devices follow MByteSwap bit in GT_PCI0_CMD Previous implementation accidentally swapped all accesses, breaking host bridge dete