On Mon, 1 Jun 2020 at 14:01, Adam Lackorzynski wrote:
> Indeed that's another option. Besides that A15+GICv3 currently just
> works with this.
Not sure how...
> So I guess the alternative is to switch to 32bit from EL3 when using an A57?
If you're using KVM then you can use -cpu host,aarch64=of
On Mon Jun 01, 2020 at 13:36:13 +0100, Peter Maydell wrote:
> On Sat, 30 May 2020 at 00:07, Adam Lackorzynski wrote:
> >
> > Initialize the CPU interface registers also
> > for Cortex-A15 and Cortex-A7 CPU models, in
> > the same way as done for 64bit CPU models.
> > This fixes usage of GICv3 in
On Sat, 30 May 2020 at 00:07, Adam Lackorzynski wrote:
>
> Initialize the CPU interface registers also
> for Cortex-A15 and Cortex-A7 CPU models, in
> the same way as done for 64bit CPU models.
> This fixes usage of GICv3 in virtualization
> contexts in 32bit configurations.
>
> Signed-off-by: Ada
Initialize the CPU interface registers also
for Cortex-A15 and Cortex-A7 CPU models, in
the same way as done for 64bit CPU models.
This fixes usage of GICv3 in virtualization
contexts in 32bit configurations.
Signed-off-by: Adam Lackorzynski
---
target/arm/cpu.c | 6 ++
1 file changed, 6 ins
