Initialize the CPU interface registers also for Cortex-A15 and Cortex-A7 CPU models, in the same way as done for 64bit CPU models. This fixes usage of GICv3 in virtualization contexts in 32bit configurations.
Signed-off-by: Adam Lackorzynski <a...@l4re.org> --- target/arm/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 32bec156f2..f525d45f6a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1972,6 +1972,9 @@ static void cortex_a7_initfn(Object *obj) cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ } @@ -2014,6 +2017,9 @@ static void cortex_a15_initfn(Object *obj) cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; define_arm_cp_regs(cpu, cortexa15_cp_reginfo); } -- 2.27.0.rc2