Hi Zhao,
On 6/9/25 5:26 AM, Zhao Liu wrote:
> Hi Dongli,
>
> Since the patch 3 was merged. I think you can rebase this series.
>
I will rebase the series.
Thank you very much!
Dongli Zhang
Would you mind suggesting any next steps on this issue?
1. Increase maximum size for "etc/acpi/rsdp", or
2. Remove host page size based alignment, and then fix any further live
migration issue?
Thank you very much!
Dongli Zhang
On 1/31/23 1:17 AM, Feng Sun wrote:
> Michael S. Tsi
ting PMC. This approach is true since Linux kernel
commit 68fb4757e867 ("KVM: x86/pmu: Defer reprogram_counter() to
kvm_pmu_handle_event"), that is, v6.2.
No Fixed tag is going to be added for the commit 0d89436786b0 ("kvm:
migrate vPMU state"), because this isn't a bug
Acked-by: Gerd Hoffmann
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
---
Changed since v2:
- Add my Signed-off-by.
Changed since v3:
- Pick new reviewed version from:
https://lore.kernel.org/all/20250401130205.2198253-8-xiaoyao...@intel.com/
I have fixed
idge perf ctrs = 0x0 (0)
number of available UMC PMCs = 0x0 (0)
active UMCs bitmask = 0x0
Disable PerfMonV2 in CPUID when PERFCORE is disabled.
Suggested-by: Zhao Liu
Fixes: 209b0ac12074 ("target/i386: Add PerfMonV2 feature bit")
Signed-off-by: D
, the meaning of pmu_version remains unchanged.
For AMD processors:
pmu_version == 1 corresponds to versions before AMD PerfMonV2.
pmu_version == 2 corresponds to AMD PerfMonV2.
Signed-off-by: Dongli Zhang
Reviewed-by: Dapeng Mi
Reviewed-by: Zhao Liu
---
Changed since v2:
- Change
g on env->features[] in future patches.
Suggested-by: Zhao Liu
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
Reviewed-by: Sandipan Das
---
Changed since v2:
- No need to check "kvm_enabled() && IS_AMD_CPU(env)".
Changed since v4:
- Add Reviewed-by from Sandipan.
target
any CPUID bit to indicate PMU
availability.
To address this, KVM_CAP_PMU_CAPABILITY is used to set KVM_PMU_CAP_DISABLE
when "-pmu" is configured.
Signed-off-by: Dongli Zhang
Reviewed-by: Xiaoyao Li
Reviewed-by: Zhao Liu
---
Changed since v1:
- Switch back to the initial implementation
sues, we propose resetting AMD PMU registers during the
VM reset process.
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
Reviewed-by: Sandipan Das
---
Changed since v1:
- Modify "MSR_K7_EVNTSEL0 + 3" and "MSR_K7_PERFCTR0 + 3" by using
AMD64_NUM_COUNTERS
kvm.enable_pmu value from the module sysfs to give a chance to
provide more information about vPMU enablement.
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
---
Changed since v2:
- Rework the code flow following Zhao's suggestion.
- Return error when:
(*kvm_enable_pmu == 'N'
try() instead of cpu_x86_cpuid(), because
CPUID has already been filled at this stage.
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
---
Changed since v1:
- Still extract the code, but call them for all CPUs.
Changed since v2:
- Use cpuid_find_entry() instead of cpu_x86_cpuid().
- Didn't
tus.
- MSR_CORE_PERF_GLOBAL_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_CTL both use
env->msr_global_ctrl.
- MSR_CORE_PERF_GLOBAL_OVF_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR
both use env->msr_global_ovf_ctrl.
No changes are needed for vmstate_msr_architectural_pmu or
pmu_enable_needed().
Signed-off-by: Dongli Zhang
Re
comment.
- Bring back global static variable 'kvm_pmu_disabled' read from
/sys/module/kvm/parameters/enable_pmu.
Changed since v4:
- Re-base on top of most recent mainline QEMU.
- Add more Reviewed-by.
- All patches are reviewed.
Xiaoyao Li (1):
kvm: Introduce kvm_arch
Hi Zhao,
On 4/25/25 1:28 AM, Zhao Liu wrote:
> On Wed, Apr 16, 2025 at 02:52:26PM -0700, Dongli Zhang wrote:
>> Date: Wed, 16 Apr 2025 14:52:26 -0700
>> From: Dongli Zhang
>> Subject: [PATCH v4 01/11] [DO NOT MERGE] i386/cpu: Consolidate the helper
>> to get Host
inux.git/commit/?id=c52ffadc65e28ab461fd055e9991e8d8106a0056
David Woodhouse has a patchset related to kvmclock and live migration.
[RFC PATCH v3 00/21] Cleaning up the KVM clock mess
https://lore.kernel.org/all/20240522001817.619072-1-dw...@infradead.org/
Maciej also fixed a similar clock unsta
kvm.enable_pmu value from the module sysfs to give a chance to
provide more information about vPMU enablement.
Signed-off-by: Dongli Zhang
---
Changed since v2:
- Rework the code flow following Zhao's suggestion.
- Return error when:
(*kvm_enable_pmu == 'N' && X86_CPU(cp
try() instead of cpu_x86_cpuid(), because
CPUID has already been filled at this stage.
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
---
Changed since v1:
- Still extract the code, but call them for all CPUs.
Changed since v2:
- Use cpuid_find_entry() instead of cpu_x86_cpuid().
- Didn't
Ping?
Any chance to accept this property? It is acked by Stefano Garzarella.
It helped me test vhost-scsi event queue and live migration recently.
https://lore.kernel.org/all/20250403063028.16045-9-dongli.zh...@oracle.com/
Thank you very much!
Dongli Zhang
On 2/11/25 8:26 AM, Stefano
g on env->features[] in future patches.
Suggested-by: Zhao Liu
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
---
Changed since v2:
- No need to check "kvm_enabled() && IS_AMD_CPU(env)".
target/i386/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/i386/cp
sues, we propose resetting AMD PMU registers during the
VM reset process.
Signed-off-by: Dongli Zhang
---
Changed since v1:
- Modify "MSR_K7_EVNTSEL0 + 3" and "MSR_K7_PERFCTR0 + 3" by using
AMD64_NUM_COUNTERS (suggested by Sandipan Das).
- Use "AMD64_NUM_COUNTERS_COR
tus.
- MSR_CORE_PERF_GLOBAL_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_CTL both use
env->msr_global_ctrl.
- MSR_CORE_PERF_GLOBAL_OVF_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR
both use env->msr_global_ovf_ctrl.
No changes are needed for vmstate_msr_architectural_pmu or
pmu_enable_needed().
Signed-off-by: Dongli Zhang
Re
Acked-by: Gerd Hoffmann
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
---
Changed since v2:
- Add my Signed-off-by.
Changed since v3:
- Pick new reviewed version from:
https://lore.kernel.org/all/20250401130205.2198253-8-xiaoyao...@intel.com/
I have fixed
ting PMC. This approach is true since Linux kernel
commit 68fb4757e867 ("KVM: x86/pmu: Defer reprogram_counter() to
kvm_pmu_handle_event"), that is, v6.2.
No Fixed tag is going to be added for the commit 0d89436786b0 ("kvm:
migrate vPMU state"), because this isn't a bug
omment.
- Bring back global static variable 'kvm_pmu_disabled' read from
/sys/module/kvm/parameters/enable_pmu.
Zhao Liu (1):
i386/cpu: Consolidate the helper to get Host's vendor [Don't merge]
Xiaoyao Li (1):
kvm: Introduce kvm_arch_pre_create_vcpu()
Dongli Zhang (9)
, the meaning of pmu_version remains unchanged.
For AMD processors:
pmu_version == 1 corresponds to versions before AMD PerfMonV2.
pmu_version == 2 corresponds to AMD PerfMonV2.
Signed-off-by: Dongli Zhang
Reviewed-by: Dapeng Mi
Reviewed-by: Zhao Liu
---
Changed since v2:
- Change
idge perf ctrs = 0x0 (0)
number of available UMC PMCs = 0x0 (0)
active UMCs bitmask = 0x0
Disable PerfMonV2 in CPUID when PERFCORE is disabled.
Suggested-by: Zhao Liu
Fixes: 209b0ac12074 ("target/i386: Add PerfMonV2 feature bit")
Signed-off-by: D
From: Zhao Liu
Extend host_cpu_vendor_fms() to help more cases to get Host's vendor
information.
Cc: Dongli Zhang
Signed-off-by: Zhao Liu
---
This patch is already queued by Paolo.
https://lore.kernel.org/all/20250410075619.145792-1-zhao1@intel.com/
I don't need to add my Sig
any CPUID bit to indicate PMU
availability.
To address this, KVM_CAP_PMU_CAPABILITY is used to set KVM_PMU_CAP_DISABLE
when "-pmu" is configured.
Signed-off-by: Dongli Zhang
Reviewed-by: Xiaoyao Li
Reviewed-by: Zhao Liu
---
Changed since v1:
- Switch back to the initial implementation
nable_pmu, NULL, NULL)) {
> -if (*kvm_enable_pmu == 'N' && X86_CPU(cpu)->enable_pmu) {
> -error_setg(errp, "Failed to enable PMU since "
> +if (*kvm_enable_pmu == 'N') {
> +warn_report("
Hi Zhao,
On 4/10/25 2:45 AM, Zhao Liu wrote:
> On Sun, Mar 30, 2025 at 06:32:29PM -0700, Dongli Zhang wrote:
>> Date: Sun, 30 Mar 2025 18:32:29 -0700
>> From: Dongli Zhang
>> Subject: [PATCH v3 10/10] target/i386/kvm: don't stop Intel PMU counters
>> X-Mailer:
index = index - MSR_F15H_PERF_CTL0;
>> +if (index & 0x1) {
>> +env->msr_gp_counters[index] = msrs[i].data;
>> +} else {
>> +env->msr_gp_evtsel[index] = msrs[i].data;
>
> This msr_gp_evtsel[] array's size is 18:
>
> #define MAX_GP_COUNTERS(MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
>
> This formula is based on Intel's MSR, it's best to add a note that the
> current size also meets AMD's needs. (No need to adjust the size, as
> it will affect migration).
I will add a comment to target/i386/cpu.h, above the definition of
MAX_GP_COUNTERS.
Thank you very much!
Dongli Zhang
Hi Zhao,
On 4/10/25 1:21 AM, Zhao Liu wrote:
> On Sun, Mar 30, 2025 at 06:32:28PM -0700, Dongli Zhang wrote:
>> Date: Sun, 30 Mar 2025 18:32:28 -0700
>> From: Dongli Zhang
>> Subject: [PATCH v3 09/10] target/i386/kvm: support perfmon-v2 for reset
>> X-Mailer: git-se
*
> + * KVM_PMU_CAP_DISABLE doesn't change the PMU
> + * behavior on Intel platform because current "pmu" property
> works
> + * as expected.
> + */
> +if ((pmu_cap & KVM_PMU_CAP_DISABLE)) {
> +ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PMU_CAPABILITY, 0,
> +KVM_PMU_CAP_DISABLE);
> +if (ret < 0) {
> +error_setg_errno(errp, -ret,
> + "Failed to set KVM_PMU_CAP_DISABLE");
> +return ret;
> }
> }
> }
>
Thank you very much! I will split based on (enable_pmu) and (!enable_pmu)
following your suggestion.
Dongli Zhang
t; Zhaoxin (including vendor "__shanghai__" and "centaurhauls")'s PMU is
> compatible with Intel, so I have some advice for this patch.
>
> 在 2025/3/3 06:00, Dongli Zhang 写道:
>> [snip]
>> +
>> +static bool is_same_vendor(CPUX86State *env)
, if kvm.enable_pmu=N.
In addition, return error when kvm.enable_pmu=N but the user wants to enable
vPMU.
Signed-off-by: Dongli Zhang
---
Changed since v2:
- Rework the code flow following Zhao's suggestion.
- Return error when:
(*kvm_enable_pmu == 'N' &&a
: Gerd Hoffmann
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
---
Changed since v2:
- Add my Signed-off-by.
accel/kvm/kvm-all.c| 5 +
include/system/kvm.h | 1 +
target/arm/kvm.c | 5 +
target/i386/kvm/kvm.c | 5 +
target/loongarch/kvm/kvm.c | 5
try() instead of cpu_x86_cpuid(), because
CPUID has already been filled at this stage.
Signed-off-by: Dongli Zhang
---
Changed since v1:
- Still extract the code, but call them for all CPUs.
Changed since v2:
- Use cpuid_find_entry() instead of cpu_x86_cpuid().
- Didn't add Reviewed-by fr
v3 patchset, it always follows the Intel path, if both guest and host are
Intel or Zhaoxin.
https://lore.kernel.org/qemu-devel/20250331013307.11937-9-dongli.zh...@oracle.com/
Thank you very much!
Dongli Zhang
instead of cpu_x86_cpuid().
- Rework the code flow of PATCH 07 related to kvm.enable_pmu=N following
Zhao's suggestion.
- Use object_property_get_int() to get CPU family.
- Add support to Zhaoxin.
Xiaoyao Li (1):
kvm: Introduce kvm_arch_pre_create_vcpu()
Dongli Zhang (9):
target/i3
tus.
- MSR_CORE_PERF_GLOBAL_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_CTL both use
env->msr_global_ctrl.
- MSR_CORE_PERF_GLOBAL_OVF_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR
both use env->msr_global_ovf_ctrl.
No changes are needed for vmstate_msr_architectural_pmu or
pmu_enable_needed().
Signed-off-by: Dongli Zhang
--
, the meaning of pmu_version remains unchanged.
For AMD processors:
pmu_version == 1 corresponds to versions before AMD PerfMonV2.
pmu_version == 2 corresponds to AMD PerfMonV2.
Signed-off-by: Dongli Zhang
Reviewed-by: Dapeng Mi
Reviewed-by: Zhao Liu
---
Changed since v2:
- Change
idge perf ctrs = 0x0 (0)
number of available UMC PMCs = 0x0 (0)
active UMCs bitmask = 0x0
Disable PerfMonV2 in CPUID when PERFCORE is disabled.
Suggested-by: Zhao Liu
Fixes: 209b0ac12074 ("target/i386: Add PerfMonV2 feature bit")
Signed-off-by: D
any CPUID bit to indicate PMU
availability.
To address this, KVM_CAP_PMU_CAPABILITY is used to set KVM_PMU_CAP_DISABLE
when "-pmu" is configured.
Signed-off-by: Dongli Zhang
Reviewed-by: Xiaoyao Li
Reviewed-by: Zhao Liu
---
Changed since v1:
- Switch back to the initial implementation
g on env->features[] in future patches.
Suggested-by: Zhao Liu
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
---
Changed since v2:
- No need to check "kvm_enabled() && IS_AMD_CPU(env)".
target/i386/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/i386/cp
sues, we propose resetting AMD PMU registers during the
VM reset process.
Signed-off-by: Dongli Zhang
---
Changed since v1:
- Modify "MSR_K7_EVNTSEL0 + 3" and "MSR_K7_PERFCTR0 + 3" by using
AMD64_NUM_COUNTERS (suggested by Sandipan Das).
- Use "AMD64_NUM_COUNTERS_COR
ode.
No Fixed tag is going to be added for the commit 0d89436786b0 ("kvm:
migrate vPMU state"), because this isn't a bugfix.
Signed-off-by: Dongli Zhang
---
target/i386/kvm/kvm.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm
tdp_mmu? Or the legacy
perf-based vPMU is going to be purged from the most recent kernel?
If they can coexist, how about add property to QEMU control between
legacy/modern? i.e. by default use legacy and change to modern as default in the
future once the feature is stable.
Thank you very much!
Dongli
CAPABILITY and prior v5.18)?
>
> Strictly speaking, only the earlier AMD PMUs are still AVAILABLE at this
> point, as the other platforms, have CPUIDs to indicate PMU enablement.
> So for the latter (which I understand is most of the cases nowadays),
> there's no reason to assume that the PMUs are still working when the CPUIDs
> are corrupted...
>
> There is no perfect solution for pre-v5.18 kernel... But while not breaking
> compatibility, again IMO, we need the logic to be self-consistent, i.e.
> any time the user does not enable vPMU (enable_pmu = false), it should be
> assumed that vPMU does not work.
>
Sure. That makes coding easier, with less assumptions.
Thank you very much!
Dongli Zhang
this check should also involve Zhaoxin CPU, so cc
>>> zhaoxin guys for double check.
>>
>> Sure for both here and below 'ditto'. Thank you very much!
>
> Per the Linux commit 3a4ac121c2cac, Zhaoxin mostly follows Intel
> Architectural PerfMon-v2. Afterall, before this patch, these PMU things
> didn't check any vendor, so I suppose vPMU may could work for Zhaoxin as
> well. Therefore, its' better to consider Zhaoxin when you check Intel
> CPU, which can help avoid introducing some regressions.
>
Thank you very much!
zhaoxin_pmu_init() looks self explanatory.
Dongli Zhang
>enable_pmu = false. (That is, "-cpu host,-pmu").
- But for KVM prior v5.18 that KVM_CAP_PMU_CAPABILITY doesn't exist.
There is no way to disable vPMU. To determine based on only
"!cpu->enable_pmu" doesn't work.
It works only when "!cpu->enable_pmu" and KVM_CAP_PMU_CAPABILITY exists.
We may still need a static global variable here to indicate where
"kvm.enable_pmu=N" (as discussed in PATCH 07).
>
>> +if (IS_INTEL_CPU(env)) {
>
> Zhaoxin also supports architectural PerfMon in 0xa.
>
> I'm not sure if this check should also involve Zhaoxin CPU, so cc
> zhaoxin guys for double check.
Sure for both here and below 'ditto'. Thank you very much!
Dongli Zhang
Hi Zhao,
On 3/9/25 11:14 PM, Zhao Liu wrote:
> On Sun, Mar 02, 2025 at 02:00:15PM -0800, Dongli Zhang wrote:
>> Date: Sun, 2 Mar 2025 14:00:15 -0800
>> From: Dongli Zhang
>> Subject: [PATCH v2 07/10] target/i386/kvm: query kvm.enable_pmu parameter
>> X-Mailer: git-se
Hi Zhao,
On 3/9/25 11:14 PM, Zhao Liu wrote:
> On Sun, Mar 02, 2025 at 02:00:15PM -0800, Dongli Zhang wrote:
>> Date: Sun, 2 Mar 2025 14:00:15 -0800
>> From: Dongli Zhang
>> Subject: [PATCH v2 07/10] target/i386/kvm: query kvm.enable_pmu parameter
>> X-Mailer: git-se
; + */
>> +static uint32_t has_pmu_version;
>
> The "has_" prefix sounds like a boolean type. So what about "pmu_version"?
Sure. I will change to pmu_version.
Thank you very much!
Dongli Zhang
>
> Others look good to me,
>
> Reviewed-by: Zhao Liu
>
>
uid(0x8001) to determine PERFCORE.
https://lore.kernel.org/all/20250302220112.17653-9-dongli.zh...@oracle.com/
(Otherwise, we may use ((env->features[FEAT_8000_0001_ECX] &
CPUID_EXT3_PERFCORE), but I prefer something consistent)
3. In PATCH 09/10 (AMD PerfMonV2), we need cpuid(0x8022) to query the
PerfMonV2 support, and the number of PMU counters.
https://lore.kernel.org/all/20250302220112.17653-10-dongli.zh...@oracle.com/
Thank you very much!
Dongli Zhang
eck to x86_cpu_expand_features(), so this patch can focus on correctly
> defining the current dependency relationship.
That means I don't need to change anything except:
1. Remove "kvm_enabled() && IS_AMD_CPU(env)" since the bit is reserved by
Intel.
2. Add your Reviewed-by.
Thank you very much!
Dongli Zhang
>
> With the above nit fixed,
>
> Reviewed-by: Zhao Liu
>
>
>
Hi Zhao,
On 3/5/25 6:46 AM, Zhao Liu wrote:
> On Sun, Mar 02, 2025 at 02:00:11PM -0800, Dongli Zhang wrote:
>> Date: Sun, 2 Mar 2025 14:00:11 -0800
>> From: Dongli Zhang
>> Subject: [PATCH v2 03/10] [DO NOT MERGE] kvm: Introduce
>> kvm_arch_pre_create_vcpu()
>>
gt;
>> Maybe we can rename has_pmu_cap to pmu_cap as well.
>
> Yes, I agree.
>
Thanks both of you very much!
I also need to modify PATCH 08/10 where has_pmu_cap is used.
[PATCH v2 08/10] target/i386/kvm: reset AMD PMU registers during VM reset
Dongli Zhang
Hi Francesco,
On 3/5/25 3:41 AM, Francesco Lavra wrote:
> On 2025-03-02 at 22:00, Dongli Zhang wrote:
>> +static bool is_same_vendor(CPUX86State *env)
>> +{
>> +static uint32_t host_cpuid_vendor1;
>> +static uint32_t host_cpuid_vendor2;
>> +s
Hi Dapeng,
On 3/4/25 11:35 PM, Mi, Dapeng wrote:
>
> On 3/3/2025 6:00 AM, Dongli Zhang wrote:
>> The kvm_put_msrs() sets the MSRs using KVM_SET_MSRS. The x86 KVM processes
>> these MSRs one by one in a loop, only saving the config and triggering the
>> KVM_REQ_PMU request
Hi Xiaoyao,
On 3/4/25 6:40 AM, Xiaoyao Li wrote:
> On 3/3/2025 6:00 AM, Dongli Zhang wrote:
>> When the PERFCORE is disabled with "-cpu host,-perfctr-core", it is
>> reflected in in guest dmesg.
>>
>> [ 0.285136] Performance Events: AMD PMU driver.
>
&
Hi Xiaoyao,
On 3/2/25 5:59 PM, Xiaoyao Li wrote:
> On 3/3/2025 6:00 AM, Dongli Zhang wrote:
>> Currently, AMD PMU support isn't determined based on CPUID, that is, the
>> "-pmu" option does not fully disable KVM AMD PMU virtualization.
>>
>> To minim
ode.
No Fixed tag is going to be added for the commit 0d89436786b0 ("kvm:
migrate vPMU state"), because this isn't a bugfix.
Signed-off-by: Dongli Zhang
---
target/i386/kvm/kvm.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm
any CPUID bit to indicate PMU
availability.
To address this, KVM_CAP_PMU_CAPABILITY is used to set KVM_PMU_CAP_DISABLE
when "-pmu" is configured.
Signed-off-by: Dongli Zhang
---
Changed since v1:
- Switch back to the initial implementation with "-pmu".
https://lore.kernel.org
idge perf ctrs = 0x0 (0)
number of available UMC PMCs = 0x0 (0)
active UMCs bitmask = 0x0
Disable PerfMonV2 in CPUID when PERFCORE is disabled.
Suggested-by: Zhao Liu
Fixes: 209b0ac12074 ("target/i386: Add PerfMonV2 feature bit")
Signed-off-by: Dongli
From: Xiaoyao Li
Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent
work prior to create any vcpu. This is for i386 TDX because it needs
call TDX_INIT_VM before creating any vcpu.
The specific implemnet of i386 will be added in the future patch.
Signed-off-by: Xiaoyao Li
Acked-by:
, the meaning of has_pmu_version remains unchanged.
For AMD processors:
has_pmu_version == 1 corresponds to versions before AMD PerfMonV2.
has_pmu_version == 2 corresponds to AMD PerfMonV2.
Signed-off-by: Dongli Zhang
---
target/i386/kvm/kvm.c | 49 ---
1
#x27;, if kvm.enable_pmu=N.
Signed-off-by: Dongli Zhang
---
target/i386/kvm/kvm.c | 16
1 file changed, 16 insertions(+)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index e895d22f94..efba3ae7a4 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kv
uot;-pmu" but not a global "pmu-cap-disabled" for KVM_PMU_CAP_DISABLE.
- Also use sysfs kvm.enable_pmu=N to determine if PMU is supported.
- Some changes to PMU register limit calculation.
Xiaoyao Li (1):
kvm: Introduce kvm_arch_pre_create_vcpu()
Dongli Zhang (9):
target/i386:
The initialization of 'has_architectural_pmu_version',
'num_architectural_pmu_gp_counters', and
'num_architectural_pmu_fixed_counters' is unrelated to the process of
building the CPUID.
Extract them out of kvm_x86_build_cpuid().
No functional change.
Signed-off
g on env->features[] in future patches.
Suggested-by: Zhao Liu
Signed-off-by: Dongli Zhang
---
target/i386/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b6d6167910..61a671028a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
tus.
- MSR_CORE_PERF_GLOBAL_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_CTL both use
env->msr_global_ctrl.
- MSR_CORE_PERF_GLOBAL_OVF_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR
both use env->msr_global_ovf_ctrl.
No changes are needed for vmstate_msr_architectural_pmu or
pmu_enable_needed().
Signed-off-by: Dongli Zhang
--
sues, we propose resetting AMD PMU registers during the
VM reset process.
Signed-off-by: Dongli Zhang
---
Changed since v1:
- Modify "MSR_K7_EVNTSEL0 + 3" and "MSR_K7_PERFCTR0 + 3" by using
AMD64_NUM_COUNTERS (suggested by Sandipan Das).
- Use "AMD64_NUM_COUNTE
de)
>>>>
>>>> Hi Dongli,
>>>>
>>>> On Mon, Nov 04, 2024 at 01:40:17AM -0800, Dongli Zhang wrote:
>>>>> Date: Mon, 4 Nov 2024 01:40:17 -0800
>>>>> From: Dongli Zhang
>>>>> Subject: [PATCH 2/7] target/i386/kvm
age02
Signed-off-by: Dongli Zhang
---
hw/scsi/vhost-scsi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/scsi/vhost-scsi.c b/hw/scsi/vhost-scsi.c
index 8039d13fd9..d3a260f6a7 100644
--- a/hw/scsi/vhost-scsi.c
+++ b/hw/scsi/vhost-scsi.c
@@ -359,6 +359,9 @@ static const Property v
5zZnDp1b1gVmO-DdpYxMvO1hlH9owAHV5UMT$
>
>
Thank you very much for the reminder!
Dongli Zhang
nction by other patches,
including the initialization of both Intel and AMD PMU infortmation (PerfMonV2).
Thank you very much!
Dongli Zhang
>
>> if (((env->cpuid_version >> 8)&0xF) >= 6
>> && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
>> (CPUID_MCE | CPUID_MCA)) {
>> --
>> 2.39.3
>>
Although the unsupported MSR write doesn't trigger any issue (thanks to
msrs_to_save_pmu[]), I agree this is the bug that I will address in v2.
Thanks to the reminder, indeed I have noticed another issue to be addressed in
v2: something unexpected may happen if we migrate from old KVM to new KVM
(assuming same QEMU versions).
Suppose one user never notice "-pmu" doesn't work on old AMD KVM, but still add
"-pmu" to QEMU command line.
old AMD KVM: "-pmu" doesn't take effect, due to the lack of
KVM_CAP_PMU_CAPABILITY.
new AMD KVM: "-pmu" takes effect.
After the migration, the vPMU won't work any longer from guest's perspective.
> implementation without pmu-cap-disabled (which was suggested before) to save
> guest-visible state during migration.
Yes, I am going to revert back to my previous solution with "-pmu".
Thanks everyone's suggestion on "-pmu" vs. "pmu-cap-disabled". To finalize the
decision helps move forward.
Would you mind clarify "without pmu-cap-disabled (which was suggested before) to
save guest-visible state during migration."?
Would you mean the compatibility issue between old QEMU version (without
"pmu-cap-disabled") and new QEMU version (with "pmu-cap-disabled")?
Thank you very much!
Dongli Zhang
Hi Sandipan,
On 11/8/24 5:09 AM, Sandipan Das wrote:
> On 11/4/2024 3:10 PM, Dongli Zhang wrote:
[snip]
>> + * separate set of addresses for the selector and counter
>> + * registers. Additionally, the address of the next selector or
>> +
Hi Maksim,
On 11/7/24 1:00 PM, Maksim Davydov wrote:
>
>
> On 11/4/24 12:40, Dongli Zhang wrote:
>> QEMU uses the kvm_get_msrs() function to save Intel PMU registers from KVM
>> and kvm_put_msrs() to restore them to KVM. However, there is no support for
>> A
Hi Zhao,
On 11/6/24 11:52 PM, Zhao Liu wrote:
> (+Dapang & Zide)
>
> Hi Dongli,
>
> On Mon, Nov 04, 2024 at 01:40:17AM -0800, Dongli Zhang wrote:
>> Date: Mon, 4 Nov 2024 01:40:17 -0800
>> From: Dongli Zhang
>> Subject: [PATCH 2/7] target/i386/kvm
tatic int __init amd_core_pmu_init(void)
1404 {
1405 union cpuid_0x8022_ebx ebx;
1406 u64 even_ctr_mask = 0ULL;
1407 int i;
1408
1409 if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
1410 return 0;
If you don't mind, I will send the v2 with your Suggested-by.
Thank you very much!
Dongli Zhang
ith PerfMonV2).
I will make it more readable in v2 following your suggestion.
Thank you very much!
Dongli Zhang
, the meaning of has_pmu_version remains unchanged.
For AMD processors:
has_pmu_version == 1 corresponds to versions before AMD PerfMonV2.
has_pmu_version == 2 corresponds to AMD PerfMonV2.
Signed-off-by: Dongli Zhang
---
target/i386/kvm/kvm.c | 49 ---
1
sues, we propose resetting AMD PMU registers during the
VM reset process.
Signed-off-by: Dongli Zhang
---
target/i386/cpu.h | 8 +++
target/i386/kvm/kvm.c | 156 +-
2 files changed, 161 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.h b/t
n only once for the first vCPU.
Additionally, the code extracted from kvm_x86_build_cpuid() is unrelated to
the process of building the CPUID.
Signed-off-by: Dongli Zhang
---
target/i386/kvm/kvm.c | 71 +++
1 file changed, 44 insertions(+), 27 deletions(-)
diff -
ode.
No Fixed tag is going to be added for the commit 0d89436786b0 ("kvm:
migrate vPMU state"), because this isn't a bugfix.
Signed-off-by: Dongli Zhang
---
target/i386/kvm/kvm.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm
idge perf ctrs = 0x0 (0)
number of available UMC PMCs = 0x0 (0)
active UMCs bitmask = 0x0
Disable PerfMonV2 in cpuid when PERFCORE is disabled.
Fixes: 209b0ac12074 ("target/i386: Add PerfMonV2 feature bit")
Signed-off-by: Dongli Zhang
---
target/
nto the VM kernel:
[...] Uhhuh. NMI received for unknown reason 30 on CPU 0.
To resolve these issues, we propose resetting AMD PMU registers during the
VM reset process
Dongli Zhang (7):
target/i386: disable PerfMonV2 when PERFCORE unavailable
target/i386/kvm: introduce 'pmu-cap-disabled&
tus.
- MSR_CORE_PERF_GLOBAL_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_CTL both use
env->msr_global_ctrl.
- MSR_CORE_PERF_GLOBAL_OVF_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR
both use env->msr_global_ovf_ctrl.
No changes are needed for vmstate_msr_architectural_pmu or
pmu_enable_needed().
Signed-off-by: Dongli Zhang
--
re currently
supports only x86 hosts, as KVM_CAP_PMU_CAPABILITY is used exclusively for
x86 systems.
Signed-off-by: Dongli Zhang
---
Another previous solution to re-use '-cpu host,-pmu':
https://lore.kernel.org/all/20221119122901.2469-1-dongli.zh...@oracle.com/
accel/kvm/kvm-all.c
I: slot 1 is not valid for virtio-net-pci, parent device only allows
plugging into slot 0.
Fix the issue by moving the verification into an independent 'if'
statement.
Fixes: 3f1e1478db2d ("enable multi-function hot-add")
Reported-by: Aswin Unnikrishnan
Signed-off-by: Dong
=limit012,file=libvirt-1-filter
\
-netdev user,id=user0,hostfwd=tcp::5028-:22 \
-device
virtio-net-pci,netdev=user0,id=net0,mac=52:54:00:12:34:56,bus=pci.0,addr=0x3 \
-monitor stdio
(qemu) info status
(qemu) savevm snapshot1
(qemu) loadvm snapshot1
Dongli Zhang
On 3/28/24 03:50, Chun Feng Wu wrote
/byapr18mb2791df7e6c0f61e2d8698e8fa0...@byapr18mb2791.namprd18.prod.outlook.com/
Thank you very much!
Dongli Zhang
On 3/21/24 08:57, Jonah Palmer wrote:
> The goal of these patches is to add support to a variety of virtio and
> vhost devices for the VIRTIO_F_IN_ORDER transport feature. This feature
> indicates
_INSERT_HEAD(&memset_contexts, context, next);
> +return 0;
> }
>
> if (!use_madv_populate_write) {
> -sigbus_memset_context = &context;
> +sigbus_memset_context = context;
> }
>
> qemu_mutex_lock(&page_m
al_err
-> error_reportf_err()
-> error_vprepend()
-> g_string_append(newmsg, (*errp)->msg) --> (*errp) is NULL
In addition, add ": " at the end of other error_reportf_err() logs.
Fixes: 7962e432b4e4 ("vhost-user-scsi: support reconnect to backend")
Signed-off-by
BILITY only for
x86.
Cc: Joe Jin
Cc: Like Xu
Cc: Denis V. Lunev
Signed-off-by: Dongli Zhang
---
This is to resurrect the patch to disable PMU. I split the patchset and
send the patch to disable PMU.
Changed since v1:
[PATCH 1/3] kvm: introduce a helper before creating the 1st vcpu
https://l
Hi Juan,
On 10/30/23 09:31, Juan Quintela wrote:
> Dongli Zhang wrote:
>> While the default "info lapic" always synchronizes cpu state ...
>>
>> mon_get_cpu()
>> -> mon_get_cpu_sync(mon, true)
>>-> cpu_synchronize_state(cpu)
>&
Hi David,
Thank you very much for the Reviewed-by in another thread.
I have re-based the patch and sent again.
https://lore.kernel.org/all/20231026211938.162815-1-dongli.zh...@oracle.com/
Dongli Zhang
On 10/26/23 09:39, Dongli Zhang wrote:
> Hi David,
>
> On 10/26/23 08:39, David
ent.
The cpu state should be synchronized when apic-id is available. Otherwise
the "info lapic " always returns stale data.
Reference:
https://lore.kernel.org/all/20211028155457.967291-19-berra...@redhat.com/
Cc: Joe Jin
Signed-off-by: Dongli Zhang
Reviewed-by: Daniel P. Berrangé
.. and resent by Daniel as part of another patchset (after review):
https://lore.kernel.org/qemu-devel/20211028155457.967291-19-berra...@redhat.com/
This utility is helpful for the diagnostic of loss of interrupt issue.
Dongli Zhang
> } else {
> cs = mon_get_cpu(mon);
> }
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