Re: [qemu PATCH 2/3] target/riscv/cpu.c: add 'ssstrict' to riscv,isa

ISA_EXT_DATA_ENTRY(ssstrict, PRIV_VERSION_1_12_0, has_priv_1_12), > ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), > ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), > ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), > -- > 2.49.0 > > Reviewed-by: Andrew Jones

Re: [PATCH v3 4/4] hw/riscv/server_platform_ref.c: add riscv-iommu-sys

-by: Daniel Henrique Barboza > --- > hw/riscv/Kconfig | 1 + > hw/riscv/server_platform_ref.c | 78 -- > 2 files changed, 75 insertions(+), 4 deletions(-) > Reviewed-by: Andrew Jones

Re: [PATCH v3 3/4] hw/riscv: Add server platform reference machine

On Wed, May 28, 2025 at 05:01:28PM -0300, Daniel Henrique Barboza wrote: > From: Fei Wu > > The RISC-V Server Platform specification[1] defines a standardized set > of hardware and software capabilities, that portable system software, > such as OS and hypervisors can rely on being present in a RI

Re: [PATCH v3 1/4] target/riscv/cpu.c: remove 'bare' condition for .profile

(def->profile) { > assert(profile_extends(def->profile, mcc->def->profile)); > -assert(mcc->def->bare); > mcc->def->profile = def->profile; > } > if (def->misa_mxl_max) { > -- > 2.49.0 > Reviewed-by: Andrew Jones

Re: [PATCH v3 2/4] target/riscv: Add server platform reference cpu

On Wed, May 28, 2025 at 05:01:27PM -0300, Daniel Henrique Barboza wrote: > From: Fei Wu > > The harts requirements of RISC-V server platform [1] require RVA23 ISA > profile support, plus Sv48, Svadu, H, Sscofmpf etc. This patch provides > a virt CPU type (rvsp-ref) as compliant as possible. > >

Re: [PATCH v4] target/riscv/kvm: add satp mode for host cpu

/qemu/-/issues/2931 > Signed-off-by: Meng Zhuo I gave my r-b on the last version of this patch (please include those when posting again without major changes), here it is again Reviewed-by: Andrew Jones drew > --- > target/riscv/cpu.c | 3 +-- > target/riscv/cpu.h

Re: [PATCH 1/3] target/riscv/tcg: restrict satp_mode changes in cpu_set_profile

ote a situation where we'll set mmu=on without a virtual > memory mode, which is a mistake. > > Only touch 'mmu' and satp_mode if the profile is being enabled. > > Suggested-by: Andrew Jones > Fixes: 55398025e7 ("target/riscv: add satp_mode profile support") &

Re: [PATCH 2/3] target/riscv/tcg: decouple profile enablement from user prop

-1396,7 +1403,7 @@ static void cpu_get_profile(Object *obj, Visitor *v, > const char *name, > static void riscv_cpu_add_profiles(Object *cpu_obj) > { > for (int i = 0; riscv_profiles[i] != NULL; i++) { > -const RISCVCPUProfile *profile = riscv_profiles[i]; > +RISCVCPUProfile *profile = riscv_profiles[i]; > > object_property_add(cpu_obj, profile->name, "bool", > cpu_get_profile, cpu_set_profile, > @@ -1408,7 +1415,7 @@ static void riscv_cpu_add_profiles(Object *cpu_obj) > * case. > */ > if (profile->enabled) { > -object_property_set_bool(cpu_obj, profile->name, true, NULL); > +riscv_cpu_set_profile(RISCV_CPU(cpu_obj), profile, true); > } > } > } > -- > 2.49.0 > Reviewed-by: Andrew Jones

Re: [PATCH 3/3] target/riscv: add profile->present flag

t;name; > -parent_enabled = object_property_get_bool(OBJECT(cpu), parent_name, > NULL); > -profile->enabled = parent_enabled; > +profile->present = parent->present; > } > > static void riscv_cpu_validate_profile(RISCVCPU *cpu, > @@ -910,7 +905,7 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu, > } > } > > -profile->enabled = profile_impl; > +profile->present = profile_impl; > > riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent); > riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent); > -- > 2.49.0 > Otherwise, Reviewed-by: Andrew Jones

Re: [PATCH] target/i386: Fix #GP error code for INT instructions

Ping? On 12/03/2025 12:06 am, Andrew Cooper wrote: > While the (intno << shift) expression is correct for indexing the IDT based on > whether Long Mode is active, the error code itself was unchanged with AMD64, > and is still the index with 3 bits of metadata in the bottom. > &g

Re: [PATCH v3] target/riscv/kvm: add satp mode for host cpu

On Tue, May 20, 2025 at 01:58:45PM +0200, Andrew Jones wrote: > On Tue, May 20, 2025 at 06:41:03PM +0800, Meng Zhuo wrote: > > This patch adds host satp mode while kvm/host cpu satp mode is not > > set. > > > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2

Re: [PATCH v3] target/riscv/kvm: add satp mode for host cpu

bject *cpu_obj) > kvm_riscv_init_machine_ids(cpu, &kvmcpu); > kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); > kvm_riscv_init_cfg(cpu, &kvmcpu); > +kvm_riscv_init_satp_mode(cpu, &kvmcpu); > > kvm_riscv_destroy_scratch_vcpu(&kvmcpu); > } > @@ -1980,7 +1998,7 @@ static bool kvm_cpu_realize(CPUState *cs, Error **errp) > } > } > > - return true; > +return true; > } > > void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > -- > 2.39.5 > > Otherwise, Reviewed-by: Andrew Jones

Re: [PATCH RFC] target: riscv: Fix satp mode initialization based on profile

On Tue, May 20, 2025 at 07:50:15AM -0300, Daniel Henrique Barboza wrote: > > > On 5/20/25 4:50 AM, Andrew Jones wrote: > > On Mon, May 19, 2025 at 02:15:05PM -0300, Daniel Henrique Barboza wrote: > > > > > > > > > On 5/19/25 1:35 PM, Andrew Jones wr

Re: [PATCH RFC] target: riscv: Fix satp mode initialization based on profile

On Mon, May 19, 2025 at 02:15:05PM -0300, Daniel Henrique Barboza wrote: > > > On 5/19/25 1:35 PM, Andrew Jones wrote: > > On Mon, May 19, 2025 at 09:48:14AM -0300, Daniel Henrique Barboza wrote: > > > > > > > > > On 5/16/25 9:23 AM, Alexandre Ghiti

Re: [PATCH RFC] target: riscv: Fix satp mode initialization based on profile

On Mon, May 19, 2025 at 09:48:14AM -0300, Daniel Henrique Barboza wrote: > > > On 5/16/25 9:23 AM, Alexandre Ghiti wrote: > > The satp mode is set using the svXX properties, but that actually > > restricts the satp mode to the minimum required by the profile and > > prevents the use of higher sat

Re: [PATCH v5 8/9] target/riscv/kvm: read/write KVM regs via env size

bit CSR in a > 32 bit field when running in a 64 bit CPU. > > To prevent that, change the current logic to honor the size of the QEMU > storage instead of the KVM CSR reg. > > Suggested-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza > --- > target/ris

Re: [PATCH v4 8/9] target/riscv/kvm: read/write KVM regs via env size

bit CSR in a > 32 bit field when running in a 64 bit CPU. > > To prevent that, change the current logic to honor the size of the QEMU > storage instead of the KVM CSR reg. > > Signed-off-by: Daniel Henrique Barboza > Suggested-by: Andrew Jones > --- > target/riscv

Re: [PATCH v4 0/9] target/riscv/kvm: CSR related fixes

On Mon, Apr 28, 2025 at 04:23:14PM -0300, Daniel Henrique Barboza wrote: > Hi, > > In this new version a change was made in patch 8. Instead of changing > scounteren to target_ulong, change the current logic to honor the QEMU > env storage instead of the KVM reg size. > > This will make QEMU the

Re: [PATCH] target/riscv: add satp mode for kvm host cpu

On Mon, Apr 28, 2025 at 03:37:26PM +0200, Radim Krčmář wrote: > 2025-04-28T14:08:59+02:00, Andrew Jones : > > On Mon, Apr 28, 2025 at 11:30:36AM +0200, Radim Krčmář wrote: > >> 2025-04-28T09:00:55+02:00, Andrew Jones : > >> > On Sun, Apr 27, 2025 at 09:25:57PM +0800,

Re: [PATCH] target/riscv: add satp mode for kvm host cpu

On Mon, Apr 28, 2025 at 11:30:36AM +0200, Radim Krčmář wrote: > 2025-04-28T09:00:55+02:00, Andrew Jones : > > On Sun, Apr 27, 2025 at 09:25:57PM +0800, Meng Zhuo wrote: > >> This patch adds host satp mode while kvm/host cpu satp mode is not > >> set. > > > &g

Re: [PATCH] target/riscv: add satp mode for kvm host cpu

On Sun, Apr 27, 2025 at 09:25:57PM +0800, Meng Zhuo wrote: > This patch adds host satp mode while kvm/host cpu satp mode is not > set. Huh, the KVM side[1] was written for this purpose, but it appears we never got a QEMU side merged. [1] commit 2776421e6839 ("RISC-V: KVM: provide UAPI for host SA

Re: [PATCH v3 8/9] target/riscv: widen scounteren to target_ulong

On Fri, Apr 25, 2025 at 01:02:02PM -0300, Daniel Henrique Barboza wrote: > We want to support scounteren as a KVM CSR. The KVM UAPI defines every > CSR size as target_ulong, and our env->scounteren is fixed at 32 bits. > > The other existing cases where the property size does not match the KVM > r

Re: [PATCH v3 8/9] target/riscv: widen scounteren to target_ulong

KVM to read/write the > scounteren CSR without any surprises. > > Aside from bumping the version of the RISCVCPU vmstate no other > behavioral changes are expected. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.h | 9 ++++- > target/riscv/machine.c | 6 +++--- > 2 files changed, 11 insertions(+), 4 deletions(-) > Reviewed-by: Andrew Jones

Re: [PATCH v2 9/9] target/riscv/kvm: add scounteren CSR

On Fri, Apr 25, 2025 at 08:37:05AM -0300, Daniel Henrique Barboza wrote: > Now that CPURISCVState::scounteren is a target_ulong, add support for > the scounteren KVM CSR. > > Reported-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/kvm/kvm-c

Re: [PATCH v2 8/9] target/riscv: widen (m|s)counteren to target_ulong

On Fri, Apr 25, 2025 at 08:37:04AM -0300, Daniel Henrique Barboza wrote: > We want to support scounteren as a KVM CSR. The KVM UAPI defines every > CSR size as target_ulong, and our env->scounteren is fixed at 32 bits. > > The other existing cases where the property size does not match the KVM > r

Re: [PATCH v2 7/9] target/riscv/kvm: add senvcfg CSR

On Fri, Apr 25, 2025 at 08:37:03AM -0300, Daniel Henrique Barboza wrote: > We're missing the senvcfg CSRs which is already present in the > KVM UAPI. > > Reported-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/kvm/kvm-cpu.c | 2 ++ >

Re: [PATCH v2 6/9] target/riscv/kvm: do not read unavailable CSRs

since we > @@ -1226,6 +1281,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, > KVMScratchCPU *kvmcpu) > } > > kvm_riscv_check_sbi_dbcn_support(cpu, reglist); > +kvm_riscv_read_csr_cfg(reglist); > } > > static void riscv_init_kvm_registers(Object *cpu_obj) > @@ -1239,7 +1295,7 @@ static void riscv_init_kvm_registers(Object *cpu_obj) > > kvm_riscv_init_machine_ids(cpu, &kvmcpu); > kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); > -kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); > +kvm_riscv_init_cfg(cpu, &kvmcpu); > > kvm_riscv_destroy_scratch_vcpu(&kvmcpu); > } > -- > 2.49.0 > Otherwise, Reviewed-by: Andrew Jones

Re: [PATCH v2 5/9] target/riscv/kvm: add kvm_csr_cfgs[]

r_cfg); > +} else { > +g_assert_not_reached(); > +} > > -KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); > -KVM_RISCV_SET_CSR(cs, env, sie, env->mie); > -KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); > -KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); > -KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); > -KVM_RISCV_SET_CSR(cs, env, scause, env->scause); > -KVM_RISCV_SET_CSR(cs, env, stval, env->stval); > -KVM_RISCV_SET_CSR(cs, env, sip, env->mip); > -KVM_RISCV_SET_CSR(cs, env, satp, env->satp); > +ret = kvm_set_one_reg(cs, csr_cfg->kvm_reg_id, ®); > +if (ret) { > +return ret; > +} > +} > > return 0; > } > -- > 2.49.0 > Otherwise, Reviewed-by: Andrew Jones

Re: [PATCH v2 4/9] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() in a macro

s) > return ret; > } > > -id = RISCV_CONFIG_REG(env, marchid); > +id = RISCV_CONFIG_REG(marchid); > ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); > if (ret != 0) { > return ret; > } > > -id = RISCV_CONFIG_REG(env, mimpid); > +id = RISCV_CONFIG_REG(mimpid); > ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); > > return ret; > @@ -1911,7 +1894,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, > Error **errp) > if (cpu->cfg.ext_zicbom && > riscv_cpu_option_set(kvm_cbom_blocksize.name)) { > > -reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, > +reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, > kvm_cbom_blocksize.kvm_reg_id); > reg.addr = (uint64_t)&val; > ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); > @@ -1930,7 +1913,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, > Error **errp) > if (cpu->cfg.ext_zicboz && > riscv_cpu_option_set(kvm_cboz_blocksize.name)) { > > -reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, > +reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, > kvm_cboz_blocksize.kvm_reg_id); > reg.addr = (uint64_t)&val; > ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); > -- > 2.49.0 > Otherwise, Reviewed-by: Andrew Jones

Re: [PATCH v2 3/9] target/riscv/kvm: turn u32/u64 reg functions in macros

_FP_F_REG(idx) KVM_RISCV_REG_ID_U32(KVM_REG_RISCV_FP_F, idx) > > -#define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) > +#define RISCV_FP_D_REG(idx) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_FP_D, idx) > > #define RISCV_VECTOR_CSR_REG(env, name) \ > kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ > -- > 2.49.0 > Otherwise, Reviewed-by: Andrew Jones

Re: [PATCH v2 1/9] target/riscv/kvm: minor fixes/tweaks

| 29 ++--- > 1 file changed, 14 insertions(+), 15 deletions(-) > Reviewed-by: Andrew Jones

Re: [PATCH v2 2/9] target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()

On Fri, Apr 25, 2025 at 08:36:58AM -0300, Daniel Henrique Barboza wrote: > 'reglist' is being g+malloc'ed but never freed. g_malloc'ed > > Reported-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/kvm

Re: [PATCH 2/2] hw/riscv/virt.c: change default CPU to 'max'

+1920,7 @@ static void virt_machine_class_init(ObjectClass *oc, > void *data) > mc->desc = "RISC-V VirtIO board"; > mc->init = virt_machine_init; > mc->max_cpus = VIRT_CPUS_MAX; > -mc->default_cpu_type = TYPE_RISCV_CPU_BASE; > +mc->default_cpu_type = TYPE_RISCV_CPU_MAX; > mc->block_default_type = IF_VIRTIO; > mc->no_cdrom = 1; > mc->pci_allow_0_address = true; > -- > 2.49.0 > Reviewed-by: Andrew Jones

Re: [PATCH 4/7] target/riscv/kvm: add kvm_csr_cfgs[]

On Wed, Apr 23, 2025 at 04:45:29PM -0300, Daniel Henrique Barboza wrote: > > > On 4/23/25 12:15 PM, Andrew Jones wrote: ... > > if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) == sizeof(uint32_t)) { > > kvm_cpu_csr_set_u32(cpu, csr_cfg, reg); > > } else if (KV

Re: [PATCH 7/7] target/riscv/kvm: reset 'scounteren' with host val

On Thu, Apr 17, 2025 at 09:48:39AM -0300, Daniel Henrique Barboza wrote: > The Linux kernel, up until at least version 6.12, has issues with a KVM > guest setting scounteren to 0 during reset. No error will be thrown > during boot, but trying to use rdtime in the guest (by executing 'ping' > for ex

Re: [PATCH 6/7] target/riscv/kvm: add missing KVM CSRs

On Thu, Apr 17, 2025 at 09:48:38AM -0300, Daniel Henrique Barboza wrote: > We're missing scounteren and senvcfg CSRs, both already present in the > KVM UAPI. > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Andrew Jones The patch changed enough that it's n

Re: [PATCH 5/7] target/riscv/kvm: do not read unavailable CSRs

On Thu, Apr 17, 2025 at 09:48:37AM -0300, Daniel Henrique Barboza wrote: > [1] reports that commit 4db19d5b21 broke a KVM guest running kernel 6.6. > This happens because the kernel does not know 'senvcfg', making it > unable to boot because QEMU is reading/wriiting it without any checks. > > Afte

Re: [PATCH 4/7] target/riscv/kvm: add kvm_csr_cfgs[]

On Thu, Apr 17, 2025 at 09:48:36AM -0300, Daniel Henrique Barboza wrote: > At this moment we're not checking if the host has support for any > specific CSR before doing get/put regs. This will cause problems if the > host KVM doesn't support it (see [1] as an example). > > We'll use the same appro

Re: [PATCH-for-10.0 1/2] hw/misc/aspeed_scu: Set MemoryRegionOps::impl::access_size to 32-bit

entations are 32-bit. > Set min/max access_size accordingly. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Andrew Jeffery

Re: [PATCH for-10.1] hw/riscv: do not mark any machine as default

On Fri, Apr 04, 2025 at 02:37:32PM +0200, Philippe Mathieu-Daudé wrote: > On 4/4/25 13:30, Daniel Henrique Barboza wrote: > > > > > > On 4/4/25 2:50 AM, Alistair Francis wrote: > > > On Fri, Mar 28, 2025 at 2:16 AM Philippe Mathieu-Daudé > > > wrote: > > > > > > > > On 27/3/25 14:02, Daniel Hen

Re: [PATCH-for-10.0 2/2] hw/misc/aspeed_scu: Correct minimum access size for AST2500 / AST2600

ast2500 and > ast2600 datasheets. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2636 > Signed-off-by: Joel Stanley > Reviewed-by: Troy Lee > Message-ID: <20241118021820.4928-1-j...@jms.id.au> > [PMD: Rebased, only including SCU changes] > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Andrew Jeffery

Re: [PATCH v3 3/3] target/riscv/kvm: add missing KVM CSRs

eady present in the > > > KVM UAPI. > > > > > > Signed-off-by: Daniel Henrique Barboza > > > Reviewed-by: Andrew Jones > > > > Acked-by: Alistair Francis > > This patch seems to have broken KVM acceleration for me: > > $ ./build/qemu-sy

[PATCH] target/i386: Fix #GP error code for INT instructions

ted to being told there was an error with IDT index 256 when INT $0x80 (128) was the problem instruction: ... Error: Unexpected fault 0x800d0802, #GP[IDT[256]] ... Fixes: d2fd1af76777 ("x86_64 linux user emulation") Signed-off-by: Andrew Cooper --- CC: Paolo Bonzini CC: Richa

Re: [PATCH v2 6/8] target/riscv/kvm: add CSR_SIREG and CSR_STOPEI emulation

On Mon, Feb 24, 2025 at 04:24:13PM +0800, Yong-Xuan Wang wrote: > Support user-space emulation of SIREG and STOPEI CSR with KVM > acceleration. For SIREG emulation, the SISELECT CSR value and iprio > array must be loaded before handling, and since the iprio array might > be modified, it must be wri

Re: [PATCH v2 5/8] target/riscv/kvm: rewrite kvm_riscv_handle_csr

On Mon, Feb 24, 2025 at 04:24:12PM +0800, Yong-Xuan Wang wrote: > Rewrite the kvm_riscv_handle_csr() to support additional CSR emulation > in user space with KVM acceleration. This update reuses the TCG CSR > emulation function to simplify the implementation and reduce the > redundant work. Also it

Re: [PATCH v2 8/8] hw/intc/imsic: prevent to use IMSIC when host doesn't support AIA extension

se { > +rcpu->cfg.ext_smaia = true; > +} > } > + > riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S, >riscv_imsic_rmw, imsic); > } > -- > 2.17.1 > > Reviewed-by: Andrew Jones

Re: [PATCH v2 7/8] docs: update the description about RISC-V AIA

controller > from > - the irqchip. See :ref:`riscv-aia` for more details on all available AIA > - modes. > + the in-kernel irqchip. Or the kernel irqchip can be disabled by using > + "-accel kvm,kernel-irqchip=off". In this case the ``virt`` machine will > + emulate the APLIC and IMSIC controller in user-space instead of using > in-kernel > + irqchip. See :ref:`riscv-aia` for more details on all available AIA modes. > > - aia-guests=nnn > > -- > 2.17.1 > > Reviewed-by: Andrew Jones

Re: [PATCH v2 2/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_AIA

On Mon, Feb 24, 2025 at 04:24:09PM +0800, Yong-Xuan Wang wrote: > Add KVM_REG_RISCV_CSR_AIA support to get/set the context of AIA > extension in VS mode. > > Signed-off-by: Yong-Xuan Wang > --- > target/riscv/kvm/kvm-cpu.c | 45 ++ > 1 file changed, 45 inserti

Re: [PATCH v2 4/8] target/riscv: add helper to get CSR name

R_TABLE_SIZE); > > +return csr_ops[csr_no].name; > +} > + > +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > target_ulong riscv_new_csr_seed(target_ulong new_value, > target_ulong write_mask); > > -- > 2.17.1 > > Reviewed-by: Andrew Jones

Re: [PATCH v2 3/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_SMSTATEEN

On Mon, Feb 24, 2025 at 04:24:10PM +0800, Yong-Xuan Wang wrote: > Add KVM_REG_RISCV_CSR_SMSTATEEN support to get/set the context of > Smstateen extension in VS mode. > > Signed-off-by: Yong-Xuan Wang > --- > target/riscv/kvm/kvm-cpu.c | 25 + > 1 file changed, 25 insertio

Re: [PATCH v2 1/8] target/riscv/kvm: rewrite get/set for KVM_REG_RISCV_CSR

REG(scause), env->scause); > +KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(stval), env->stval); > +KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sip), env->mip); > +KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(satp), env->satp); >

Re: [PATCH] hw/net: ftgmac100: copy eth_hdr for alignment

Hi Patrick, On Thu, 2025-02-27 at 15:42 +, Patrick Venture wrote: > eth_hdr requires 2 byte alignment > > Signed-off-by: Patrick Venture > --- >  hw/net/ftgmac100.c | 15 --- >  1 file changed, 12 insertions(+), 3 deletions(-) > > diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac10

Re: [PATCH v2 2/3] target/riscv/cpu.c: create flag for ziccrse

a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index ea8d77d06a..c93612b1da 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -360,6 +360,8 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu) > > cpu->cfg.ext_sha = r

Re: [PATCH 3/3] target/riscv/kvm: add extensions after 6.14-rc3 update

FG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), > KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), > KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), > +KVM_EXT_CFG("svvptc", ext_svvptc, KVM_RISCV_ISA_EXT_SVVPTC), > }; > > static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) > -- > 2.48.1 > > Reviewed-by: Andrew Jones

Re: [PATCH v2 3/3] target/riscv/kvm: add missing KVM CSRs

SCV_SET_CSR(cs, env, scounteren, env->scounteren); > +KVM_RISCV_SET_CSR(cs, env, senvcfg, env->senvcfg); > > return 0; > } > -- > 2.48.1 > Reviewed-by: Andrew Jones

Re: [PATCH v2 2/3] target/riscv/kvm: add kvm_riscv_reset_regs_csr()

pu->env.fdt_addr; /* a1 */ > -env->satp = 0; > -env->mie = 0; > -env->stvec = 0; > -env->sscratch = 0; > -env->sepc = 0; > -env->scause = 0; > -env->stval = 0; > -env->mip = 0; > + > +kvm_riscv_reset_regs_csr(env); > } > > void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) > -- > 2.48.1 > Reviewed-by: Andrew Jones

Re: [PATCH 2/3] target/riscv/cpu.c: create flag for ziccrse

On Tue, Feb 18, 2025 at 01:38:53PM -0300, Daniel Henrique Barboza wrote: > At this moment ziccrse is a TCG always enable ext that has no flag. KVM > will expose ziccrse to users, allowing them to turn it on/off. KVM won't allow this to be disabled, since it can't be (there's no way to turn off the

Re: [PATCH 3/3] target/riscv/kvm: reset all available KVM CSRs in kvm_reset()

On Fri, Feb 21, 2025 at 09:45:35AM +0100, Andrew Jones wrote: > On Thu, Feb 20, 2025 at 01:13:13PM -0300, Daniel Henrique Barboza wrote: > > Explictly reset env->mstatus and env->sie. > > mie was already getting set to zero, so that should have just been renamed > in the

Re: [PATCH 3/3] target/riscv/kvm: reset all available KVM CSRs in kvm_reset()

On Thu, Feb 20, 2025 at 01:13:13PM -0300, Daniel Henrique Barboza wrote: > Explictly reset env->mstatus and env->sie. mie was already getting set to zero, so that should have just been renamed in the last patch, but I still think we should drop the last patch. > Add a comment about env->mip > bei

Re: [PATCH 2/3] target/riscv/kvm: use env->sie to read/write 'sie' CSR

On Thu, Feb 20, 2025 at 01:13:12PM -0300, Daniel Henrique Barboza wrote: > Using env->sie is clearer than using env->mie. Maybe? Just as sstatus is a subset of mstatus, sip and sie can be subsets of mip and mie. However, the AIA can change sip/sie so they no longer alias mip/mie, which is why we h

Re: [PATCH 1/3] target/riscv/cpu: ignore TCG init for KVM CPUs in reset_hold

m/kvm-cpu.c > index 23ce779359..484b6afe7c 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -1603,9 +1603,6 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu) > CPURISCVState *env = &cpu->env; > int i; > > -if (!kvm_enabled()) { > -return; > -} > for (i = 0; i < 32; i++) { > env->gpr[i] = 0; > } > -- > 2.48.1 > > Reviewed-by: Andrew Jones

Re: [PATCH] aspeed: Remove duplicate typename in AspeedSoCClass

On Tue, 2025-02-18 at 08:35 +0100, Cédric Le Goater wrote: > The SoC type name is stored under AspeedSoCClass which is > redundant. Use object_get_typename() instead where needed. > > Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery

Re: [PULL 3/9] meson: Disallow 64-bit on 32-bit Xen emulation

at least, was) tied to qemu-system-i386 was using Qemu as a XenBlk <-> QCOW adapter, at which point it wasn't even really a system emulator, just a paravirtual disk implementation. This is, AIUI, what ARM wants with the xenpv machine.  If there's a better way to do this, please do say. Looking through Xen's CI, I can't see any of the ARM builds building QEMU at all.  I think it's quite possible it's not tested any more. ~Andrew

Re: [PATCH 4/8] target/riscv: add helper to get CSR name

On Mon, Feb 17, 2025 at 04:17:24PM +0800, Yong-Xuan Wang wrote: > Add a helper function to get CSR name from CSR number. > > Signed-off-by: Yong-Xuan Wang > --- > target/riscv/cpu.h | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/c

Re: [PATCH 7/8] target/riscv/kvm: rename riscv-aia to riscv-imsic

On Mon, Feb 17, 2025 at 04:17:27PM +0800, Yong-Xuan Wang wrote: > The riscv-aia property only controls the in-kernel IMSIC mode, the > emulation of AIA MSI mode is controlled by the kernel-irqchip property. > Rename the riscv-aia property to riscv-imsic to prevent the confusion. > > Signed-off-by:

答复: [PATCH v3] hw/net: cadence_gem: feat: add logic for the DISABLE_MASK bit in type2_compare_x_word_1

On Tue, 4 Feb 2025 at 22:37, Peter Maydell wrote: > On Thu, 30 Jan 2025 at 22:31, Edgar E. Iglesias > wrote: > > On Mon, Jan 27, 2025 at 8:40 AM Peter Maydell > > wrote: > >> On Thu, 19 Dec 2024 at 06:17, Andrew.Yuan > >> wrote: > >> > -rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr

Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1

   | >     |  UART11  |   |   >       | >     | >|17 |   >   | >     |  UART12  |   |   >   | >     | >|18 |   >   | >     |  |---|   >   | >     |  >   | >     > |---| > > Thanks, I'll consider this updated diagram as well while I put my own together from the other pieces of info you've provided. Andrew

Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1

On Tue, 2025-02-04 at 09:43 +, Jamin Lin wrote: > Hi Andrew, > > > -Original Message- > > From: Andrew Jeffery > > Sent: Thursday, January 30, 2025 12:20 PM > > To: Jamin Lin ; Cédric Le Goater ; > > Peter Maydell ; Steven Lee > > ; Troy Lee

Re: [PATCH v1 17/18] hw/arm/aspeed_ast27x0: Add HACE support for AST2700

On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote: > The HACE controller between AST2600 and AST2700 are almost identical. > The HACE controller registers base address starts at 0x1207_ and > its alarm interrupt is connected to GICINT4. > > Signed-off-by: Jamin Lin Revi

Re: [PATCH v1 16/18] hw/misc/aspeed_hace: Add AST2700 support

On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote: > Introduce a new ast2700 class to support AST2700. > > Signed-off-by: Jamin Lin Reviewed-by: Andrew Jeffery

Re: [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1

EED_DEV_WDT]   = 195, > +    [ASPEED_DEV_PWM]   = 195, > +    [ASPEED_DEV_LPC]   = 192, > +    [ASPEED_DEV_IBT]   = 192, > +    [ASPEED_DEV_I2C]   = 194, > +    [ASPEED_DEV_PECI]  = 197, > +    [ASPEED_DEV_ETH1]  = 196, > +    [ASPEED_DEV_ETH2]  = 196, > +    [ASPEED_DEV_ETH3]  = 196, > +    [ASPEED_DEV_HACE]  = 4, > +    [ASPEED_DEV_KCS]   = 192, > +    [ASPEED_DEV_DP]    = 28, > +    [ASPEED_DEV_I3C]   = 195, > +    [ASPEED_DEV_SDHCI] = 197, > +}; Bit of a nit, but can we sort this table? Perhaps by interrupt value? Andrew

Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1

  AST2700 A0 Design    > >   | > > > >   | > +---+ > Okay, so I think this is the diagram and discussion I asked for as documentation earlier. I still prefer it doesn't just live in a commit message, that you pull it out to a separate document that we can easily point to and evolve. I'm a little hazy on some of your notation in diagram though. Can you explain your use of pipes ("|"), plusses ("+"), the "orgates" to the left of INTC1 (what are they ORing?), and the choice of 5 lines into the "orgates[0]" box? Also why does the "orgates[0]" arrow point where it does on INTC0? Andrew

Re: [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions

ate { >  #define AST2700_A0_SILICON_REV   0x06000103U >  #define AST2720_A0_SILICON_REV   0x06000203U >  #define AST2750_A0_SILICON_REV   0x0603U > +#define AST2700_A1_SILICON_REV   0x06010103U > +#define AST2750_A1_SILICON_REV   0x06010003U These look fine. Andrew >   >  #define ASPEED_IS_AST2500(si_rev) si_rev) >> 24) & 0xff) == > 0x04) >  

Re: [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address

rther, it would be great if the documentation also described the motivation for the interrupt chaining involving involving INT128-159, INTM*, and GICINT192_201, GICINT208 and GICINT224. Clearly it's a thing, but, why? Andrew

Re: [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops

son not to make it a different type altogether? I'm not sure I like the idea of playing tricks with the memory ops. The timer model does something similar, but I was toying with the idea of removing that part of its implementation... Andrew

Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0

amp;a->intc, > TYPE_ASPEED_2700_INTC); > +    object_initialize_child(obj, "intc", &a->intc, > TYPE_ASPEED_2700_INTC0); Shouldn't we also change the propname to "intc0" (... if we're to continue with that style of naming)? Andrew

Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0

112b869124fc9d7e35ac031596.ca...@codeconstruct.com.au/ Ryan didn't like deviating from their internal documentation :( Andrew

Re: [PATCH 0/5] tests/functional: Update Aspeed OpenBMC images

On Wed, 2025-01-29 at 08:19 +0100, Cédric Le Goater wrote: > On 1/29/25 00:29, Andrew Jeffery wrote: > > Hi Cédric, > > > > On Tue, 2025-01-28 at 22:41 +0100, Cédric Le Goater wrote: > > > Hello, > > > > > > This series updates the OpenBMC firmw

Re: [PATCH 0/5] tests/functional: Update Aspeed OpenBMC images

: Introduce a witherspoon machine test >   tests/functional: Introduce a bletchley machine test The rest of the patches haven't reached my inbox. Did you send them? It also seems they're missing on lore :) https://lore.kernel.org/all/20250128214100.1196243-1-...@redhat.com/ Andrew

Re: [PATCH-for-10.1 v2 03/13] hw/arm/virt: Remove VirtMachineClass::disallow_affinity_adjustment

On Thu, Jan 16, 2025 at 03:59:34PM +0100, Philippe Mathieu-Daudé wrote: > The VirtMachineClass::disallow_affinity_adjustment > field was only used by virt-2.6 machine, which got > removed. Remove it and simplify virt_cpu_mp_affinity(). > > Signed-off-by: Philippe Mathieu-Daudé > --- > include/hw

Re: [PATCH v2] hw/riscv/virt: Add serial alias in DTB

rng_seed, sizeof(rng_seed)); > > +qemu_fdt_add_subnode(ms->fdt, "/aliases"); > + > create_fdt_flash(s, memmap); > create_fdt_fw_cfg(s, memmap); > create_fdt_pmu(s); > -- > 2.46.0 > Only fix the minor commit message issues if you need to respin for other reasons. Reviewed-by: Andrew Jones

Re: [RFC PATCH] hw/riscv/virt: Add serial alias in DTB

On Thu, Jan 16, 2025 at 09:46:29AM +0100, Vasilis Liaskovitis wrote: > This patch adds an "aliases" node with a "serial0" entry for the > single UART in the riscv64 virt machine. > > This was requested in Gitlab #2774. However, since the machine only > has one UART at the moment, it's not clear th

Re: [PATCH v3 2/7] xen: do not use '%ms' scanf specifier

NULL, NULL, "%s/%s", > + xendev->frontend_path, key);; Double ;; ~Andrew

Re: [PATCH v3 6/6] target/riscv: add RVA23S64 profile

@@ -3198,6 +3236,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, > rva22u64_profile_cpu_init), > DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, > rva22s64_profile_cpu_init), > DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, MXL_RV64, > rva23u64_profile_cpu_init), > +DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23S64, MXL_RV64, > rva23s64_profile_cpu_init), > #endif /* TARGET_RISCV64 */ > }; > > -- > 2.47.1 > Otherwise, Reviewed-by: Andrew Jones

Re: [PATCH v3 4/6] target/riscv: change priv_ver check in validate_profile()

; #endif > > if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && > -profile->priv_spec != env->priv_ver) { > +profile->priv_spec > env->priv_ver) { > profile_impl = false; > > if (send_warn) { > -- > 2.47.1 > Reviewed-by: Andrew Jones

Re: [PATCH v3 3/6] target/riscv: add profile u_parent and s_parent

s change ...like we were doing with the previous 'parent'... > does nothing for the existing profiles but will make RVA23S64 simpler. > > Suggested-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 6 -- > targ

Re: [PATCH v2] hw/intc/riscv_aplic: Remove redundant "hart_idx" masking

group_idx = hart_idx >> lhxw; > -hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw); > > addr = msicfgaddr; > addr |= ((uint64_t)(msicfgaddrH & APLIC_xMSICFGADDRH_BAPPN_MASK)) << 32; > -- > 2.34.1 > > Reviewed-by: Andrew Jones

Re: [PATCH v2 3/4] target/riscv: add RVA23U64 profile

+ > 2 files changed, 33 insertions(+) > Reviewed-by: Andrew Jones

Re: [PATCH v2 2/4] target/riscv: use RVB in RVA22U64

fsets = { > diff --git a/tests/data/acpi/riscv64/virt/RHCT > b/tests/data/acpi/riscv64/virt/RHCT > index > b14ec15e553200760a63aad65586913d31ea2edc..13c8025b868051485be5ba62974a22971a07bc6a > 100644 > GIT binary patch > delta 53 > zcmeBUp1{l%JqB1j+%-qDZl;ot1UQ&#clNpsc(ij;S > I3K$s}0ARKZK>z>% > > delta 52 > zcmbQh+{ern6Im@tvcKtP9)kwJyAsLaeHGdD3UC3&N_6yxMHMkS6EMh1pF > HMg|4|IwT82 > > -- > 2.47.1 > Reviewed-by: Andrew Jones

Re: [PATCH v2 1/4] target/riscv: add ssu64xl

> delta 48 > zcmZo;?qlW(@^B96V`N}pOqj@Jz^cQ@$e^;(o|BQSxYW#~B4@H2qXkC_BLhPoBLf2f > D`wIz- > > delta 41 > wcmeBUZe!*O@^B7mV`N}poG_8gfK`Q&kwIpoJtyPj07f&87)Az$G)4vn0JA^`U;qFB > > -- > 2.47.1 > Reviewed-by: Andrew Jones

Re: [PATCH v2 4/4] target/riscv: add RVA23S64 profile

On Tue, Jan 14, 2025 at 04:00:01PM -0300, Daniel Henrique Barboza wrote: > Add RVA23S64 as described in [1]. This profile inherits all mandatory > extensions of RVA23U64, making it a child of the U64 profile. > > A new "rva23s64" profile CPU is also added. This is the generated > riscv,isa for it

Re: [PATCH 2/4] target/riscv: use RVB in RVA22U64

On Tue, Jan 14, 2025 at 01:08:46PM -0300, Daniel Henrique Barboza wrote: > > > On 1/14/25 11:52 AM, Andrew Jones wrote: > > On Tue, Jan 14, 2025 at 10:20:10AM -0300, Daniel Henrique Barboza wrote: > > > From the time we added RVA22U64 until now the spec didn&#x

Re: [PATCH v1] hw/intc/riscv_aplic: Remove redundant masking of hart_idx in riscv_aplic_msi_send()

Drop "in riscv_aplic_msi_send()" from the patch summary to make it more concise. On Tue, Jan 14, 2025 at 10:53:19AM +0800, Huang Borong wrote: > The line "hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw);" was removed This just states what we can easily read from the patch. > because the same

Re: [PATCH 1/2] hw/riscv/riscv-iommu: Remove redundant variables

Background processing wake up signal */ > -unsigned core_exec; /* Processing thread execution actions */ > - > /* IOMMU target address space */ > AddressSpace *target_as; > MemoryRegion *target_mr; > -- > 2.43.2 > > Otherwise, Reviewed-by: Andrew Jones

Re: [PATCH 2/2] hw/riscv/riscv-iommu-bits: Remove redundant definitions

ne RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2) > -#define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0) > -#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3) > -#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12) > - > - > /* > * struct riscv_iommu_msi_pte - MSI Page Table Entry > */ > -- > 2.43.2 > > Reviewed-by: Andrew Jones

Re: [PATCH 4/4] target/riscv: add RVA23S64 profile

On Tue, Jan 14, 2025 at 10:20:12AM -0300, Daniel Henrique Barboza wrote: > Add RVA23S64 as described in [1]. This profile inherits all mandatory > extensions of RVA23U64, making it a child of the U64 profile. > > A new "rva23s64" profile CPU is also added. This is the generated > riscv,isa for it

Re: [PATCH 4/4] target/riscv: add RVA23S64 profile

On Tue, Jan 14, 2025 at 10:20:12AM -0300, Daniel Henrique Barboza wrote: > Add RVA23S64 as described in [1]. This profile inherits all mandatory > extensions of RVA23U64, making it a child of the U64 profile. > > A new "rva23s64" profile CPU is also added. This is the generated > riscv,isa for it

Re: [PATCH 3/4] target/riscv: add RVA23U64 profile

On Tue, Jan 14, 2025 at 10:20:11AM -0300, Daniel Henrique Barboza wrote: > Add RVA23U64 as described in [1]. This profile does not share all > mandatory RVA22U64 extensions so we can't use RVA22U64 as a parent. We > need to declare all mandatory extensions from scratch. But it does share all manda

Re: [PATCH 2/4] target/riscv: use RVB in RVA22U64

On Tue, Jan 14, 2025 at 10:20:10AM -0300, Daniel Henrique Barboza wrote: > From the time we added RVA22U64 until now the spec didn't declare 'RVB' > as a dependency, using zba/zbb/zbs instead. Since then the RVA22 spec > [1] added the following in the 'RVA22U64 Mandatory Extensions' section: > > "

Re: [PATCH v1 1/3] hw/timer/aspeed: Support different memory region ops

On Mon, 2024-12-16 at 15:53 +0800, Jamin Lin wrote: > It set "aspeed_timer_ops" struct which containing read and write > callbacks > to be used when I/O is performed on the TIMER region. > > Besides, in the previous design of ASPEED SOCs, the timer registers > address > space are contiguous. > >

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