[RFC v2 PATCH] docs: Enhance documentation for iommu bypass

es appear in a DRHD's device scope. Enhance the document by mentioning what could happen when bypass_iommu is used under Linux guest. For detailed qemu cmdline and guest kernel dmesg, please see: https://lore.kernel.org/qemu-devel/20240510072519.GA39314@ziqianlu-desk2/ Reported-by: Juro Bystrick

Re: [RFC PATCH] docs: Enhance documentation for iommu bypass

On Thu, May 23, 2024 at 08:52:35PM +0800, Aaron Lu wrote: > On Wed, May 22, 2024 at 08:34:13PM +0800, Aaron Lu wrote: > > > > I do not have Windows VM right now and will report back once I finished > > testing there. > > Tested with a Windows 10 VM and turnes out virt

Re: [RFC PATCH] docs: Enhance documentation for iommu bypass

On Wed, May 22, 2024 at 08:34:13PM +0800, Aaron Lu wrote: > > I do not have Windows VM right now and will report back once I finished > testing there. Tested with a Windows 10 VM and turnes out virtio pci devices always use MSI no matter vIOMMU and bypass iommu are specified or

Re: [RFC PATCH] docs: Enhance documentation for iommu bypass

On Wed, May 22, 2024 at 05:28:50AM -0400, Michael S. Tsirkin wrote: > On Wed, May 22, 2024 at 03:40:08PM +0800, Aaron Lu wrote: > > When Intel vIOMMU is used and irq remapping is enabled, using > > bypass_iommu will cause following two callstacks dumped during kernel > > boo

[RFC PATCH] docs: Enhance documentation for iommu bypass

7;s device scope. Enhance the document by mentioning what could happen when bypass_iommu is used. For detailed qemu cmdline and guest kernel dmesg, please see: https://lore.kernel.org/qemu-devel/20240510072519.GA39314@ziqianlu-desk2/ Reported-by: Juro Bystricky Signed-off-by: Aaron Lu ---

Problem with bypass iommu

Hi, When bypass iommu is used together with split irqchip, during boot, kernel would dump 2 callstacks(see attached) and the results are pci devices attached to root bus will fall back to using IOAPIC instead of MSIx. This problem was initally noticed by Juro. This only happens with kernel-irqchi

Re: [PATCH] hw/acpi: propagate vcpu hotplug after switch to modern interface

BTW: This BUG often results in intermittent OVMF Exceptions/ASSERTs as well. Thanks, -Aaron From: qemu-devel-bounces+aaron.young=oracle@nongnu.org on behalf of Aaron Young Sent: Tuesday, December 12, 2023 8:51 AM To: qemu-devel@nongnu.org Cc

[PATCH] hw/acpi: propagate vcpu hotplug after switch to modern interface

Cc: "Michael S. Tsirkin" Cc: Igor Mammedov Signed-off-by: Aaron Young --- hw/acpi/cpu_hotplug.c | 20 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/hw/acpi/cpu_hotplug.c b/hw/acpi/cpu_hotplug.c index 634bbec..6f78db0 100644 --- a/hw/acpi/cpu_hotplug.c

Re: [PATCH v3 2/8] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection

On Jun 09 13:51, Richard Henderson wrote: > On 6/9/23 10:23, Aaron Lindsay wrote: > > +static inline int isar_feature_pauth_get_features(const ARMISARegisters > > *id) > > +{ > > +if (isar_feature_aa64_pauth_arch_qarma5(id)) { > > +return FIELD_EX64(id

Re: [PATCH v3 1/8] target/arm: Add ID_AA64ISAR2_EL1

On Jun 09 13:49, Richard Henderson wrote: > On 6/9/23 10:23, Aaron Lindsay wrote: > > --- a/target/arm/hvf/hvf.c > > +++ b/target/arm/hvf/hvf.c > > @@ -847,6 +847,7 @@ static bool > > hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) > >

[PATCH v3 0/8] Implement Most ARMv8.3 Pointer Authentication Features

decoding PAC branch instructions) [0] - https://lists.nongnu.org/archive/html/qemu-devel/2023-02/msg06494.html Aaron Lindsay (8): target/arm: Add ID_AA64ISAR2_EL1 target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection target/arm: Implement v8.3 QARMA3 PAC cipher target/arm: Implement v8.3

[PATCH v3 2/8] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 65 +-- target/arm/tcg/pauth_helper.c | 2 +- 2 files changed, 63 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df04c9a9ab..22dd898577 100644 --- a/target/arm

[PATCH v3 7/8] target/arm: Implement v8.3 FPAC and FPACCOMBINE

Signed-off-by: Aaron Lindsay --- target/arm/syndrome.h | 7 +++ target/arm/tcg/pauth_helper.c | 16 2 files changed, 23 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index d27d1bc31f..bf79c539d9 100644 --- a/target/arm/syndrome.h +++ b

[PATCH v3 3/8] target/arm: Implement v8.3 QARMA3 PAC cipher

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/pauth_helper.c | 54 --- 1 file changed, 44 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index

[PATCH v3 5/8] target/arm: Implement v8.3 Pauth2

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/pauth_helper.c | 33 +++-- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index

[PATCH v3 8/8] target/arm: Add CPU property for QARMA3, enable FPACCombined by default

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 48 +++--- 2 files changed, 34 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 22dd898577..0c4c6c9c82 100644 --- a/target/arm/cpu.h

[PATCH v3 4/8] target/arm: Implement v8.3 EnhancedPAC

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/pauth_helper.c | 15 ++- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 68942015e1

[PATCH v3 1/8] target/arm: Add ID_AA64ISAR2_EL1

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 1 + target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 1 + target/arm/kvm64.c | 2 ++ 4 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 36c608f0e6..df04c9a9ab 100644 --- a/target

[PATCH v3 6/8] targer/arm: Inform helpers whether a PAC instruction is 'combined'

feature for ARMv8.3. Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson --- target/arm/tcg/helper-a64.h| 4 ++ target/arm/tcg/pauth_helper.c | 71 +++--- target/arm/tcg/translate-a64.c | 12 +++--- 3 files changed, 68 insertions(+), 19 deletions(-) diff --

Re: [PATCH v2 7/7] target/arm: Add CPU properties for most v8.3 PAC features

On Feb 22 12:14, Richard Henderson wrote: > On 2/22/23 09:35, Aaron Lindsay wrote: > > +static Property arm_cpu_pauth2_property = > > +DEFINE_PROP_BOOL("pauth2", ARMCPU, prop_pauth2, false); > > +static Property arm_cpu_pauth_fpac_property = > > +

Re: [PATCH v2 6/7] target/arm: Implement v8.3 FPAC and FPACCOMBINE

On Feb 22 11:37, Richard Henderson wrote: > On 2/22/23 09:35, Aaron Lindsay wrote: > > @@ -406,6 +421,16 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t > > ptr, uint64_t modifier, > > uint64_t xor_mask = MAKE_64BIT_MASK(bot_bit, top_b

[PATCH v3 4/8] target/arm: Implement v8.3 EnhancedPAC

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/pauth_helper.c | 15 ++- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 122c208de2

[PATCH v3 1/8] target/arm: Add ID_AA64ISAR2_EL1

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 1 + target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 1 + target/arm/kvm64.c | 2 ++ 4 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c097cae988..f0f27f259d 100644 --- a/target

[PATCH v3 8/8] target/arm: Add CPU property for QARMA3, enable FPACCombined by default

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 48 +++--- 2 files changed, 34 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 868d844d5a..80683c428f 100644 --- a/target/arm/cpu.h

[PATCH v3 7/8] target/arm: Implement v8.3 FPAC and FPACCOMBINE

Signed-off-by: Aaron Lindsay --- target/arm/syndrome.h | 7 +++ target/arm/tcg/pauth_helper.c | 16 2 files changed, 23 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index d27d1bc31f..bf79c539d9 100644 --- a/target/arm/syndrome.h +++ b

[PATCH v3 5/8] target/arm: Implement v8.3 Pauth2

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/pauth_helper.c | 33 +++-- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index

[PATCH v3 3/8] target/arm: Implement v8.3 QARMA3 PAC cipher

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/pauth_helper.c | 54 --- 1 file changed, 44 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index

[PATCH v3 0/8] Implement Most ARMv8.3 Pointer Authentication Features

code formatting fixes and logic simplifications [0] - https://lists.nongnu.org/archive/html/qemu-devel/2023-02/msg06494.html Aaron Lindsay (8): target/arm: Add ID_AA64ISAR2_EL1 target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection target/arm: Implement v8.3 QARMA3 PAC cipher targe

[PATCH v3 2/8] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 65 +-- target/arm/tcg/pauth_helper.c | 2 +- 2 files changed, 63 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f0f27f259d..868d844d5a 100644 --- a/target/arm

[PATCH v3 6/8] targer/arm: Inform helpers whether a PAC instruction is 'combined'

feature for ARMv8.3. Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson --- target/arm/helper-a64.h| 4 ++ target/arm/tcg/pauth_helper.c | 71 +++--- target/arm/tcg/translate-a64.c | 20 +- 3 files changed, 72 insertions(+), 23 deletions(-) dif

[PATCH v2 6/7] target/arm: Implement v8.3 FPAC and FPACCOMBINE

Signed-off-by: Aaron Lindsay --- target/arm/pauth_helper.c | 35 ++- target/arm/syndrome.h | 7 +++ 2 files changed, 37 insertions(+), 5 deletions(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index 96770d7860..db6cf9b5bc 100644

[PATCH v2 3/7] target/arm: Implement v8.3 EnhancedPAC

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/pauth_helper.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index f525ef7fad..a83956652f 100644 --- a/target/arm/pauth_helper.c

[PATCH v2 7/7] target/arm: Add CPU properties for most v8.3 PAC features

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 5 +++ target/arm/cpu64.c | 81 ++ 2 files changed, 72 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9c3cbc9a29..40b4631f11 100644 --- a/target/arm/cpu.h

[PATCH v2 2/7] target/arm: Implement v8.3 QARMA3 PAC cipher

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/pauth_helper.c | 50 +++ 1 file changed, 40 insertions(+), 10 deletions(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index e5206453f6..f525ef7fad 100644 --- a

[PATCH v2 0/7] Implement Most ARMv8.3 Pointer Authentication Features

vious patchset - I'm planning to await further discussion about the appropriate way to organize them before making those changes and particularly welcome further review there. -Aaron [0] https://lists.nongnu.org/archive/html/qemu-devel/2023-02/msg00660.html Aaron Lindsay (7): target/arm:

[PATCH v2 5/7] targer/arm: Inform helpers whether a PAC instruction is 'combined'

feature for ARMv8.3. Signed-off-by: Aaron Lindsay --- target/arm/helper-a64.h| 4 +++ target/arm/pauth_helper.c | 71 +++--- target/arm/translate-a64.c | 20 +-- 3 files changed, 72 insertions(+), 23 deletions(-) diff --git a/target/arm/helper-a64.h b/t

[PATCH v2 4/7] target/arm: Implement v8.3 Pauth2

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/pauth_helper.c | 32 ++-- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index a83956652f..c4ee040da7 100644 --- a/target/arm

[PATCH v2 1/7] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 61 +-- target/arm/helper.c | 4 +-- target/arm/pauth_helper.c | 2 +- 3 files changed, 61 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8cf70693be

Re: [PATCH 1/7] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection

On Feb 13 16:01, Peter Maydell wrote: > On Thu, 2 Feb 2023 at 21:13, Aaron Lindsay > wrote: > > +static inline bool isar_feature_aa64_pauth_epac(const ARMISARegisters *id) > > +{ > > +return isar_feature_pauth_get_features(id) == 0b0010; > > This should

Re: [PATCH 7/7] target/arm: Add CPU properties for most v8.3 PAC features

On Feb 13 17:11, Peter Maydell wrote: > On Thu, 2 Feb 2023 at 21:12, Aaron Lindsay > wrote: > > > > Signed-off-by: Aaron Lindsay > > --- > > target/arm/cpu.h | 5 +++ > > target/arm/cpu64.c | 81 ++ > &

Re: Lost partition tables on ide-hd + ahci drive

ests. Is there any commonality in the storage format being used? Is it qcow2? Is it network-backed? There are reports with local ZFS volumes, local LVM-Thin volumes, RBD images, qcow2 on NFS. So no pattern to be seen. Apologies for the "tier 1" questions. Thank you for your time!

[PATCH 6/7] target/arm: Implement v8.3 FPAC and FPACCOMBINE

Signed-off-by: Aaron Lindsay --- target/arm/pauth_helper.c | 26 ++ target/arm/syndrome.h | 6 ++ 2 files changed, 32 insertions(+) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index 66dc90a289..3a2772de0e 100644 --- a/target/arm

[PATCH 4/7] target/arm: Implement v8.3 Pauth2

Signed-off-by: Aaron Lindsay --- target/arm/pauth_helper.c | 29 +++-- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index a83956652f..6ebf6df75c 100644 --- a/target/arm/pauth_helper.c +++ b/target

[PATCH 2/7] target/arm: Implement v8.3 QARMA3 PAC cipher

Signed-off-by: Aaron Lindsay --- target/arm/pauth_helper.c | 48 +++ 1 file changed, 39 insertions(+), 9 deletions(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index a0c9bea06b..f525ef7fad 100644 --- a/target/arm/pauth_helper.c +++ b

[PATCH 1/7] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 57 --- target/arm/helper.c | 4 +-- target/arm/pauth_helper.c | 4 +-- 3 files changed, 58 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8cf70693be

[PATCH 7/7] target/arm: Add CPU properties for most v8.3 PAC features

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 5 +++ target/arm/cpu64.c | 81 ++ 2 files changed, 72 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9be59163ff..a9420bae67 100644 --- a/target/arm/cpu.h

[PATCH 0/7] Implement Most ARMv8.3 Pointer Authentication Features

Hello, I've taken a first pass at implementing many of the ARMv8.3 Pointer Authentication features and welcome your review. Thanks! -Aaron Aaron Lindsay (7): target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection target/arm: Implement v8.3 QARMA3 PAC cipher target/arm: Implement

[PATCH 5/7] targer/arm: Inform helpers whether a PAC instruction is 'combined'

feature for ARMv8.3. Signed-off-by: Aaron Lindsay --- target/arm/helper-a64.h| 4 +++ target/arm/pauth_helper.c | 63 -- target/arm/translate-a64.c | 20 ++-- 3 files changed, 68 insertions(+), 19 deletions(-) diff --git a/target/arm/helper-a64.h b/t

[PATCH 3/7] target/arm: Implement v8.3 EnhancedPAC

Signed-off-by: Aaron Lindsay --- target/arm/pauth_helper.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index f525ef7fad..a83956652f 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c

Re: [PATCH 1/4] plugins: fix optimization in plugin_gen_disable_mem_helpers

on. > > Related: #1381 > > Signed-off-by: Emilio Cota > --- > accel/tcg/plugin-gen.c | 26 ++ > include/qemu/plugin.h | 7 +++ > 2 files changed, 25 insertions(+), 8 deletions(-) Tested-by: Aaron Lindsay

Re: [PATCH 2/4] translator: always pair plugin_gen_insn_{start,end} calls

On Jan 08 11:47, Emilio Cota wrote: > Related: #1381 > > Signed-off-by: Emilio Cota > --- > accel/tcg/translator.c | 15 ++- > 1 file changed, 10 insertions(+), 5 deletions(-) Tested-by: Aaron Lindsay

Re: Plugin Memory Callback Debugging

Emilio, On Dec 18 00:24, Emilio Cota wrote: > On Tue, Nov 29, 2022 at 15:37:51 -0500, Aaron Lindsay wrote: > (snip) > > > Does this hint that there are cases where reset cpu->plugin_mem_cbs to > > > NULL is > > > getting optimized away, but not the code to se

Re: Plugin Memory Callback Debugging

On Nov 22 10:57, Aaron Lindsay wrote: > On Nov 21 18:22, Richard Henderson wrote: > > On 11/21/22 13:51, Alex Bennée wrote: > > > > > > Aaron Lindsay writes: > > > > > > > On Nov 15 22:36, Alex Bennée wrote: > > > > > Aaron Lindsa

Re: Plugin Memory Callback Debugging

On Nov 21 22:02, Alex Bennée wrote: > > Aaron Lindsay writes: > > > Sorry, left off the very end of my timeline: > > > > On Nov 18 16:58, Aaron Lindsay wrote: > >> I have, so far, discovered the following timeline: > >> 1. My plugin receive

Re: Plugin Memory Callback Debugging

On Nov 21 18:22, Richard Henderson wrote: > On 11/21/22 13:51, Alex Bennée wrote: > > > > Aaron Lindsay writes: > > > > > On Nov 15 22:36, Alex Bennée wrote: > > > > Aaron Lindsay writes: > > > > > I believe the code *should* alw

Re: Plugin Memory Callback Debugging

On Nov 15 22:36, Alex Bennée wrote: > Aaron Lindsay writes: > > I believe the code *should* always reset `cpu->plugin_mem_cbs` to NULL at > > the > > end of an instruction/TB's execution, so its not exactly clear to me how > > this > > is occurring. Howe

Re: Plugin Memory Callback Debugging

On Nov 15 22:36, Alex Bennée wrote: > > Aaron Lindsay writes: > > > Hello, > > > > I have been wrestling with what might be a bug in the plugin memory > > callbacks. The immediate error is that I hit the > > `g_assert_not_reached()` in the 'd

Re: Plugin Memory Callback Debugging

Sorry, left off the very end of my timeline: On Nov 18 16:58, Aaron Lindsay wrote: > I have, so far, discovered the following timeline: > 1. My plugin receives a instruction execution callback for a load >instruction. At this time, cpu->plugin_mem_cbs points to the same >me

Plugin Memory Callback Debugging

ail down the failure case and/or help in working towards an appropriate solution. Thanks! -Aaron

Re: [BUG] AArch64 boot hang with -icount and -smp >1 (iothread locking issue?)

On Oct 21 17:00, Peter Maydell wrote: > On Fri, 21 Oct 2022 at 16:48, Aaron Lindsay > wrote: > > > > Hello, > > > > I am encountering one or more bugs when using -icount and -smp >1 that I am > > attempting to sort out. My current theory is that it is an

[BUG] AArch64 boot hang with -icount and -smp >1 (iothread locking issue?)

Pavel's "replay: rewrite async event handling" commit [2]. Commits prior to that one boot successfully (neither assertions nor hangs) with `-icount 0 -smp 2`. I've looked over these two commits ([1], [2]), but it is not obvious to me how/why they might be interacting to produce the

Re: Plugins Not Reporting AArch64 SVE Memory Operations

On Mar 28 16:30, Alex Bennée wrote: > > Aaron Lindsay writes: > > > Hi folks, > > > > I see there has been some previous discussion [1] about 1.5 years ago > > around the fact that AArch64 SVE instructions do not emit any memory > > operations via the plu

Plugins Not Reporting AArch64 SVE Memory Operations

and no one else is doing it), would someone mind pointing me in the right direction to get started? Thanks! -Aaron [1] https://lists.nongnu.org/archive/html/qemu-discuss/2020-12/msg00015.html

Re: [PATCH v1 12/22] plugins: stxp test case from Aaron (!upstream)

On Feb 01 15:29, Alex Bennée wrote: > > Aaron Lindsay writes: > > > On Jan 24 20:15, Alex Bennée wrote: > >> Signed-off-by: Alex Bennée > >> Cc: Aaron Lindsay > >> Message-ID: > >> > >> --- > >> [AJB] this was for testing,

Re: [PATCH v1 12/22] plugins: stxp test case from Aaron (!upstream)

On Jan 25 09:17, Thomas Huth wrote: > On 24/01/2022 21.15, Alex Bennée wrote: > > Signed-off-by: Alex Bennée > > Cc: Aaron Lindsay > > Message-ID: > > > > --- > > [AJB] this was for testing, I think you can show the same stuff with > > the much mor

Re: [PATCH v1 12/22] plugins: stxp test case from Aaron (!upstream)

On Jan 24 20:15, Alex Bennée wrote: > Signed-off-by: Alex Bennée > Cc: Aaron Lindsay > Message-ID: > > --- > [AJB] this was for testing, I think you can show the same stuff with > the much more complete execlog now. Is it true that execlog can also reproduce the dupl

Re: plugins: Missing Store Exclusive Memory Accesses

gize, I had apparently gotten farther behind upstream than I realized since originally encountering this. I tried the latest upstream code and am now able to observe the same thing as you. Somewhere between v6.1.0 and now, the original issue I reported has been resolved. However, I am not sure reporting loads for a store exclusive makes sense to me here, either. My understanding is that the stxp needs to check if it still has exclusive access and QEMU's implementation results in the extra loads, but I would expect that the plugin interface would only report architectural loads. Is there any obvious way to omit the loads from the plugin interface here? -Aaron

Re: plugins: Missing Store Exclusive Memory Accesses

Executing PC: 0x400718 Executing PC: 0x40071c Executing PC: 0x400720 >From this, I believe the ldxp instruction at PC 0x400710 is reporting two memory accesses but the stxp instruction at 0x400714 is not. -Aaron --- stxp.c --- void stxp_issue_demo(); int main() {

Re: plugins: Missing Store Exclusive Memory Accesses

On Sep 22 16:22, Aaron Lindsay wrote: > On Sep 21 16:28, Aaron Lindsay wrote: > > On Sep 17 12:05, Alex Bennée wrote: > > > Aaron Lindsay writes: > > > > I recently noticed that the plugin interface does not appear to be > > > > emit

Re: plugins: Missing Store Exclusive Memory Accesses

On Sep 21 16:28, Aaron Lindsay wrote: > On Sep 17 12:05, Alex Bennée wrote: > > Aaron Lindsay writes: > > > I recently noticed that the plugin interface does not appear to be > > > emitting callbacks to functions registered via > > > `qemu_plugin_register_vcpu_

Re: plugins: Missing Store Exclusive Memory Accesses

On Sep 17 12:05, Alex Bennée wrote: > Aaron Lindsay writes: > > I recently noticed that the plugin interface does not appear to be > > emitting callbacks to functions registered via > > `qemu_plugin_register_vcpu_mem_cb` for AArch64 store exclusives. This > > would incl

Re: plugins: Missing Store Exclusive Memory Accesses

On Sep 17 12:05, Alex Bennée wrote: > Aaron Lindsay writes: > > In looking at QEMU's source, I *think* this is because the > > `gen_store_exclusive` function in translate-a64.c is not making the same > > calls to `plugin_gen_mem_callbacks` & company that are bei

plugins: Missing Store Exclusive Memory Accesses

xed together. Thanks for any help, Aaron

Re: [PATCH] plugins: Fix physical address calculation for IO regions

For reference, this patch is intended to address this conversation: https://lists.nongnu.org/archive/html/qemu-devel/2021-07/msg01293.html This appears to be better than the previous version in my testing, but I absolutely welcome being told there is a better way to solve this! Thanks! -Aaron

[PATCH] plugins: Fix physical address calculation for IO regions

The address calculation for IO regions introduced by commit 787148bf928a54b5cc86f5b434f9399e9737679c Author: Aaron Lindsay plugins: Expose physical addresses instead of device offsets is not always accurate. Use the more correct MemoryRegionSection.offset_within_address_space. --- plugins

Re: Plugin virtual-to-physical translation incorrect for some IO accesses

On Jul 07 07:35, Aaron Lindsay wrote: > On Jul 07 09:53, Philippe Mathieu-Daudé wrote: > > On 7/6/21 11:56 PM, Aaron Lindsay wrote: > > > On Jul 06 23:10, Philippe Mathieu-Daudé wrote: > > >> +Peter/Paolo > > >> > > >> On 7/6/21 10:47 PM,

Re: Plugin virtual-to-physical translation incorrect for some IO accesses

On Jul 07 09:53, Philippe Mathieu-Daudé wrote: > On 7/6/21 11:56 PM, Aaron Lindsay wrote: > > On Jul 06 23:10, Philippe Mathieu-Daudé wrote: > >> +Peter/Paolo > >> > >> On 7/6/21 10:47 PM, Aaron Lindsay wrote: > >>> Hello, > >>> &

Re: Plugin virtual-to-physical translation incorrect for some IO accesses

On Jul 06 23:10, Philippe Mathieu-Daudé wrote: > +Peter/Paolo > > On 7/6/21 10:47 PM, Aaron Lindsay wrote: > > Hello, > > > > I previously supplied a patch which modified the plugin interface such > > that it will return physical addresses for IO regions [0]. How

Plugin virtual-to-physical translation incorrect for some IO accesses

s there a reason we should not do that? Thanks! -Aaron [0] https://lists.nongnu.org/archive/html/qemu-devel/2021-03/msg03137.html

[Bug 1926996] Re: qemu-user clone syscall fails

clone_test (x86_64) ** Attachment added: "clone_test (x86_64)" https://bugs.launchpad.net/qemu/+bug/1926996/+attachment/5494470/+files/clone_test -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/192

[Bug 1926996] Re: qemu-user clone syscall fails

clone_test aarch64 binary ** Attachment added: "clone_test (aarch64)" https://bugs.launchpad.net/qemu/+bug/1926996/+attachment/5494467/+files/clone_test -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/b

[Bug 1926996] [NEW] qemu-user clone syscall fails

Public bug reported: qemu-user fails to emulate clone() (https://linux.die.net/man/2/clone). The architecture doesn't seem to matter, tho I've mostly been testing aarch64. Attached is clone_test.c that demonstrates the problem. Running it natively looks like this: $ bin/x86_64/clone_test The va

[Bug 1926996] Re: qemu-user clone syscall fails

clone_test (aarch64) ** Attachment added: "clone_test (aarch64)" https://bugs.launchpad.net/qemu/+bug/1926996/+attachment/5494469/+files/clone_test -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1

[Bug 1926996] Re: qemu-user clone syscall fails

clone_test x86_64 binary ** Description changed: qemu-user fails to emulate clone() (https://linux.die.net/man/2/clone). The architecture doesn't seem to matter, tho I've mostly been testing aarch64. Attached is clone_test.c that demonstrates the problem. Running it natively looks li

[Bug 1926202] Re: qemu-user can't run some ppc binaries

Thanks for looking into this. What reference did you use to check which ISA "cmpb" is in? -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1926202 Title: qemu-user can't run some ppc binaries Status

Re: [RFC] tcg plugin: Additional plugin interface

;-) > >> > >> Yes the implementation would be a simple helper which could be called > >> from a callback - I don't think we need to limit it to just insn_exec. I > >> think the challenge is proving a non-ugly API that works cleanly across > >> all the

[Bug 1926202] Re: qemu-user can't run some ppc binaries

helloworld-centos.static.ppc is attached as part of comment #2 -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1926202 Title: qemu-user can't run some ppc binaries Status in QEMU: New Bug descrip

[Bug 1926202] Re: qemu-user can't run some ppc binaries

** Attachment added: "ppc binary that crashes qemu-user" https://bugs.launchpad.net/qemu/+bug/1926202/+attachment/5492563/+files/helloworld-centos.static.ppc ** Description changed: qemu-user v6.0.0-rc5, built in static mode, will crash for certain ppc binaries. It seems to have somethin

[Bug 1926202] [NEW] qemu-user can't run some ppc binaries

Public bug reported: qemu-user v6.0.0-rc5, built in static mode, will crash for certain ppc binaries. It seems to have something to do with glibc for some Centos versions. The problem is easiest to see with statically-linked binaries. The attached Dockerfile shows how to produce a ppc binary th

Re: [PATCH v1 11/14] plugins: expand kernel-doc for instruction query and instrumentation

On Mar 16 13:48, Alex Bennée wrote: > Aaron Lindsay writes: > > On Mar 12 17:28, Alex Bennée wrote: > >> + * @insn: opaque instruction handle from qemu_plugin_tb_get_insn() > >> + * > >> + * Returns: hardware (physical) address of instruction > >>

Re: [PATCH v1 08/14] plugins: add qemu_plugin_cb_flags to kernel-doc

On Mar 16 13:40, Alex Bennée wrote: > > Aaron Lindsay writes: > > > On Mar 12 17:28, Alex Bennée wrote: > >> Also add a note to explain currently they are unused. > >> > >> Signed-off-by: Alex Bennée > > > > I'm personally inte

Re: [PATCH v1 12/14] plugins: expand kernel-doc for memory query and instrumentation

On Mar 12 17:28, Alex Bennée wrote: > Signed-off-by: Alex Bennée Small comment below, but otherwise: Reviewed-by: Aaron Lindsay > --- > include/qemu/qemu-plugin.h | 35 --- > 1 file changed, 28 insertions(+), 7 deletions(-) > > diff --git a

Re: [PATCH v1 09/14] plugins: add qemu_plugin_id_t to kernel-doc

On Mar 12 17:28, Alex Bennée wrote: > Signed-off-by: Alex Bennée Reviewed-by: Aaron Lindsay > --- > include/qemu/qemu-plugin.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h > index c98866a637..5ac6

Re: [PATCH v1 08/14] plugins: add qemu_plugin_cb_flags to kernel-doc

On Mar 12 17:28, Alex Bennée wrote: > Also add a note to explain currently they are unused. > > Signed-off-by: Alex Bennée I'm personally interested in one clarification below, but don't think that affects my: Reviewed-by: Aaron Lindsay > --- > includ

Re: [PATCH v1 06/14] plugins: expand the callback typedef kernel-docs

On Mar 12 17:28, Alex Bennée wrote: > Signed-off-by: Alex Bennée One nit below, but otherwise: Reviewed-by: Aaron Lindsay > --- > include/qemu/qemu-plugin.h | 25 ++--- > 1 file changed, 22 insertions(+), 3 deletions(-) > > diff --git a/include/qe

Re: [PATCH v1 11/14] plugins: expand kernel-doc for instruction query and instrumentation

address of instruction > + */ > uint64_t qemu_plugin_insn_vaddr(const struct qemu_plugin_insn *insn); > + > +/** > + * qemu_plugin_insn_haddr() - return vaddr of instruction Copypasta: s/vaddr/haddr/ ? > + * @insn: opaque instruction handle from qemu_plugin_tb_get_insn() > + * > + * Returns: hardware (physical) address of instruction > + */ > void *qemu_plugin_insn_haddr(const struct qemu_plugin_insn *insn); Is this the physical address of the instruction on the host or target? -Aaron

Re: [PATCH v1 10/14] plugins: expand inline exec kernel-doc documentation.

On Mar 12 17:28, Alex Bennée wrote: > Remove the extraneous @cb parameter and document the non-atomic nature > of the INLINE_ADD_U64 operation. > > Signed-off-by: Alex Bennée Reviewed-by: Aaron Lindsay > --- > include/qemu/qemu-plugin.h | 12 +++- > 1 file c

Re: [PATCH v1 07/14] plugins: expand the typedef kernel-docs for translation

On Mar 12 17:28, Alex Bennée wrote: > Signed-off-by: Alex Bennée Reviewed-by: Aaron Lindsay > --- > include/qemu/qemu-plugin.h | 17 ++--- > 1 file changed, 10 insertions(+), 7 deletions(-) > > diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qem

Re: [PATCH v1 05/14] plugins: cleanup kernel-doc for qemu_plugin_install

On Mar 12 17:28, Alex Bennée wrote: > kernel-doc doesn't like multiple Note sections. Also add an explicit > Return. > > Signed-off-by: Alex Bennée Reviewed-by: Aaron Lindsay > --- > include/qemu/qemu-plugin.h | 12 ++-- > 1 file changed, 6 insertions(+)

Re: [PATCH v1 04/14] plugins: expand kernel-doc for qemu_info_t

On Mar 12 17:28, Alex Bennée wrote: > It seems kernel-doc struggles a bit with typedef structs but with > enough encouragement we can get something out of it. > > Signed-off-by: Alex Bennée Reviewed-by: Aaron Lindsay > --- > include/qemu/qemu-plugin.h | 22 ++

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