On 17/7/25 11:38, Djordje Todorovic wrote:
Introduce P8700 CPU by MIPS.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 15 +++
target/riscv/cpu_vendorid.h | 1 +
3 files changed, 17 insertions
Hi,
On 17/7/25 11:38, Djordje Todorovic wrote:
I addressed several comments in this version, major ones:
- split CPC / CMGCR into separated changes
- split CPS into a separated change
- added functional tests for boston-aia board
Djordje Todorovic (14):
hw/misc: Add RISC-V CMGCR
Hi,
On 17/7/25 11:38, Djordje Todorovic wrote:
Add functional test for Boston AIA board. The P8700 RISC-V based
CPU by MIPS supports it at the moment.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
tests/functional/meson.build| 1 +
tests/functional/test_risc
On 17/7/25 11:38, Djordje Todorovic wrote:
Since there is no pch_gbe emulation, we could be using func other
than 0 when adding new devices to specific boards.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/pci/pci.c | 15 +--
1 file changed, 9 insertions(+)
On 17/7/25 11:38, Djordje Todorovic wrote:
Add support for the Coherent Processing System for RISC-V.
This enables SMP support for RISC-V boards that require
cache-coherent multiprocessor systems.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/misc/Kconfig| 5 +
On 17/7/25 11:38, Djordje Todorovic wrote:
Add RISC-V implementation of the Cluster Power Controller (CPC) device.
It is based on the existing MIPS CPC implementations but adapted for
RISC-V systems.
The CPC device manages power control for CPU clusters in RISC-V
systems.
This is needed for the
On 8/8/25 18:00, Philippe Mathieu-Daudé wrote:
On 17/7/25 11:38, Djordje Todorovic wrote:
Add RISC-V implementation of the Coherent Manager Global Control
Register (CMGCR) device. It is based on the existing MIPS CMGCR
implementation but adapted for RISC-V systems.
The CMGCR device provides
On 17/7/25 11:38, Djordje Todorovic wrote:
Add RISC-V implementation of the Coherent Manager Global Control
Register (CMGCR) device. It is based on the existing MIPS CMGCR
implementation but adapted for RISC-V systems.
The CMGCR device provides global system control for multi-core
configurations
On 17/7/25 11:38, Djordje Todorovic wrote:
Add MIPS P8700 ldp, lwp, sdp, swp instructions.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 +
target/riscv/cpu_cfg.h| 2 +-
target/riscv/cpu_cfg_fields.h.inc
On 17/7/25 11:38, Djordje Todorovic wrote:
Add RISC-V implementation of the Coherent Manager Global Control
Register (CMGCR) device. It is based on the existing MIPS CMGCR
implementation but adapted for RISC-V systems.
The CMGCR device provides global system control for multi-core
configurations
On 17/7/25 11:38, Djordje Todorovic wrote:
This is needed for riscv based CPUs by MIPS since those may have
sparse hart-ID layouts. ACLINT and APLIC still assume a dense
range, and if a hart is missing, this causes NULL derefs.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
On 8/8/25 10:08, Markus Armbruster wrote:
We added @error_warn some two years ago in commit 3ffef1a55ca (error:
add global &error_warn destination). It has multiple issues:
* error.h's big comment was not updated for it.
* Function contracts were not updated for it.
* ERRP_GUARD() is unaware
Hi Markus,
On 8/8/25 10:08, Markus Armbruster wrote:
tcg_region_init() calls one of qemu_mprotect_rwx(),
qemu_mprotect_rw(), and mprotect(), then reports failure with
error_setg_errno(&error_fatal, errno, ...).
The use of &error_fatal is undesirable. qapi/error.h advises:
* Please don't err
On 8/8/25 10:08, Markus Armbruster wrote:
qapi/error.h advises:
* Please don't error_setg(&error_fatal, ...), use error_report() and
* exit(), because that's more obvious.
Do that.
The error message starts with "internal error: ", so maybe this should
assert() instead.
Cc: Steve Sistare
scv64: ../hw/sd/ssi-sd.c:160: ssi_sd_transfer: Assertion
`s->arglen > 0' failed.
Reported-by: Guenter Roeck
Fixes: 775616c3ae8 ("Partial SD card SPI mode support")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/ssi-sd.c | 4
1 file changed, 4 insertions(+)
diff --g
-off-by: Philippe Mathieu-Daudé
---
tests/functional/test_riscv64_sifive_u.py | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/tests/functional/test_riscv64_sifive_u.py
b/tests/functional/test_riscv64_sifive_u.py
index dc4cb8a4a96..f7ab1abfd56 100755
Trivial fix for the issue reported by Guenter here:
https://lore.kernel.org/qemu-devel/5b2dc427-f0db-4332-a997-fe0c82415...@roeck-us.net/
- Return dummy byte when no card is connected
- Add a test
Philippe Mathieu-Daudé (2):
hw/sd/ssi-sd: Return noise (dummy byte) when no card connected
On 7/8/25 18:06, Guenter Roeck wrote:
On Wed, Aug 06, 2025 at 09:22:46AM +0200, Philippe Mathieu-Daudé wrote:
On 6/8/25 08:39, Michael Tokarev wrote:
Philippe, do you think this series is something which should
go to stable-10.0 (LTS) branch? I'm not sure for the impact if
it is not ap
nrom/multiboot.S | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
anged, 5 insertions(+), 6 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 3/8/25 09:38, Akihiko Odaki wrote:
On 2025/08/02 23:45, Michael Tokarev wrote:
On 02.08.2025 17:21, Michael Tokarev wrote:
This field is a fixed-size buffer (number of elements is MAX_VLAN,
known at build time). There's no need to allocate it dynamically,
it can be made an integral part of
On 2/8/25 16:21, Michael Tokarev wrote:
The only user of this macro was VirtIONet.vlans, which has been
converted to regular VMSTATE_BUFFER.
Signed-off-by: Michael Tokarev
---
include/migration/vmstate.h | 9 -
1 file changed, 9 deletions(-)
Yay!
Reviewed-by: Philippe Mathieu
ngs_reference.html#memory64
Signed-off-by: Kohei Tokunaga
---
configure | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 6/8/25 17:49, Kohei Tokunaga wrote:
The wasm builds are tested for 3 targets: wasm32, wasm64(-sMEMORY64=1) and
wasm64(-sMEMORY64=2). The CI builds the containers using the same Dockerfile
(emsdk-wasm-cross.docker) with different build args.
Signed-off-by: Kohei Tokunaga
---
.gitlab-ci.d/bu
On 28/7/25 15:41, Mohamed Mediouni wrote:
Misc changes needed for HVF vGIC enablement.
Signed-off-by: Mohamed Mediouni
---
accel/hvf/hvf-all.c| 44 ++
accel/stubs/hvf-stub.c | 1 +
hw/arm/virt.c | 16 +-
hw/intc/arm_
sert_hvf_ok() calls, so adding more isn't
really helping. Anyhow,
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
ld value is non-zero and valid, PMU register accesses are
emulated by the framework.
The ID_AA64DFR0_EL1 register can be modified via hv_vcpu_set_sys_reg API.
Signed-off-by: Mohamed Mediouni
---
target/arm/hvf/hvf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Ph
On 28/7/25 15:41, Mohamed Mediouni wrote:
When starting up the VM at EL2, more sysregs are available. Sync the state of
those.
In addition, sync the state of the EL1 physical timer when the vGIC is used,
even
if running at EL1. However, no OS running at EL1 is expected to use those
registers.
lue?
+ahcf->midr = 0x610f;
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
On 28/7/25 15:41, Mohamed Mediouni wrote:
This opens up the door to nested virtualisation support.
Signed-off-by: Mohamed Mediouni
---
hw/intc/arm_gicv3_hvf.c | 722
hw/intc/meson.build | 1 +
2 files changed, 723 insertions(+)
create mode 10
On 6/8/25 09:56, Michael Tokarev wrote:
Commit c0ddcb2cbc146e introduced the test which uses cache=direct
mode, without checking if the scratch filesystem supports O_DIRECT.
A subsequent commit, afeb002e0ad49d, tried to fix that issue, but
instead of checking for o_direct, it checked for
`_suppor
On 6/8/25 09:30, Kevin Wolf wrote:
Am 05.08.2025 um 19:56 hat Michael Tokarev geschrieben:
On 05.08.2025 20:23, Philippe Mathieu-Daudé wrote:
diff --git a/tests/qemu-iotests/tests/mirror-sparse b/tests/qemu-
iotests/tests/mirror-sparse
index cfcaa600ab..19843a622c 100755
--- a/tests/qemu
On 6/8/25 08:39, Michael Tokarev wrote:
Philippe, do you think this series is something which should
go to stable-10.0 (LTS) branch? I'm not sure for the impact if
it is not applied, though, - what do we miss in this case?
Only 2 machines use a SD card wired over SPI lines:
$ git grep '"ssi-
nal/{test_microblaze_s3adsp1800.py =>
microblaze/test_s3adsp1800.py} (100%)
create mode 100644 tests/functional/microblazeel/meson.build
rename tests/functional/{test_microblazeel_s3adsp1800.py =>
microblazeel/test_s3adsp1800.py} (92%)
Reviewed-by: Philippe Mathieu-Daudé
On 5/8/25 15:56, Thomas Huth wrote:
On 04/08/2025 10.31, Philippe Mathieu-Daudé wrote:
Hi Thomas,
On 1/8/25 17:12, Thomas Huth wrote:
From: Thomas Huth
The tests/functional folder has become quite crowded, thus move the
mips tests into a target-specific subfolder.
Signed-off-by: Thomas
Hi Kohei,
On 4/8/25 14:57, Kohei Tokunaga wrote:
Currently there are some engines that don't support wasm64 (e.g. unsupported
on Safari[1]). To mitigate this issue, the configure script allows the user
to use Emscripten's compatibility feature, "-sMEMORY64=2" flag[2].
Emscripten's "-sMEMORY64=2
deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
+
scripts/tracetool/format/ust_events_h.py | 1 +
8 files changed, 9 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
-
1 file changed, 7 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 5/8/25 22:03, Daniel P. Berrangé wrote:
Signed-off-by: Daniel P. Berrangé
---
scripts/tracetool/format/c.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
pch_pic.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
-8372-b62b3bcd0...@codethink.co.uk/
Inspired-by: Guenter Roeck
Inspired-by: Ben Dooks
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Richard Henderson
Message-Id: <20250804133406.17456-12-phi...@linaro.org>
---
MAINTAINERS | 1 +
tests/functional/meson
of addressable IDs field for
CPUID.01H.EBX[23:16]")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3061
Signed-off-by: Zhao Liu
Reviewed-by: Michael Tokarev
Tested-by: Michael Tokarev
Message-ID: <20250804053548.1808629-1-zhao1@intel.com>
Signed-off-by: Philippe Mathieu-Daudé
While spi_cmd_SEND_OP_COND() is incomplete, sd_cmd_SEND_OP_COND()
is, except it doesn't return the correct value in SPI mode.
Correct and use, removing the need for spi_cmd_SEND_OP_COND().
Fixes: 775616c3ae8 ("Partial SD card SPI mode support")
Signed-off-by: Philippe Mathieu-
y the size filled
in the buffer. Convert the returned type to unsigned and remove
the few unreachable lines in callers.
This allow to check for possible overflow in sd_do_command().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250804133406.174
SD card mode is a superset of its state (SDState::state),
no need to migrate it.
Use sd_mode() to get the SDCardModes from the SDCardStates.
Fixes: 50a5be6c3d5 ("hw/sd.c: add SD card save/load support")
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Richard Henderson
spi_cmd_SEND_CSD() and spi_cmd_SEND_CID() are very
similar. Factor the common code as spi_cmd_SEND_CxD().
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Richard Henderson
Message-Id: <20250804133406.17456-9-phi...@linaro.org>
---
hw/sd/sd.c | 19 ++-
1 file chang
Fixes: af151d50eac24 "hw/pci-host/gpex-acpi: Use
build_pci_host_bridge_osc_method"
Signed-off-by: Eric Auger
Reported-by: Michael Tokarev
Reviewed-by: Michael Tokarev
Message-ID: <20250804152008.247673-1-eric.au...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i
In SPI mode, R2 is a 2-byte value.
Implement in spi_response_r2_make() and
return SPI R2 in the SEND_STATUS commands.
Reported-by: Guenter Roeck
Fixes: 775616c3ae8 ("Partial SD card SPI mode support")
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Richard Henderson
nter Roeck
Reported-by: Ben Dooks
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Richard Henderson
Message-Id: <20250804133406.17456-10-phi...@linaro.org>
---
hw/sd/sd.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index ee81dc09991..22f30997713 10
-sd.c.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Richard Henderson
Message-Id: <20250804133406.17456-5-phi...@linaro.org>
---
hw/sd/sd.c | 32 ---
hw/sd/ssi-sd.c | 87 --
2 files changed, 35 insertions(+), 84 del
Unfortunately when adding sd_cmd_to_sendingdata() in commit
f486bf7d109 we neglected to return any possible error. Fix.
Fixes: f486bf7d109 ("hw/sd/sdcard: Introduce sd_cmd_to_sendingdata and
sd_generic_read_byte")
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
In SPI mode, SWITCH_FUNCTION is valid in all mode
(except the IDLE one).
Fixes: 775616c3ae8 ("Partial SD card SPI mode support")
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Richard Henderson
Message-Id: <20250804133406.17456-8-phi...@linaro.org>
---
hw/sd/sd.c | 10 ++
Set @rsplen once before switching to fill the response buffer.
This will allow to assert in a single place that the buffer is
big enough to be filled with the response.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250804133406.17456-3-phi...@linaro.
selecting Kconfig ACPI_PCI
- Fix legacy Intel SMT info removing 'x-vendor-cpuid-only-v2' property check
Eric Auger (1):
hw/i386/microvm: Explicitly select ACPI_PCI
Philippe Mathieu-Daudé (11):
hw/sd/sdcard: Do
On 1/8/25 14:28, Michael Tokarev wrote:
This test uses cache.direct=true, but does not check if O_DIRECT
is supported by the underlying filesystem, and fails, for example,
on a tmpfs (which is rather common on various auto-builders, in CI,
etc).
Fix this by using _require_o_direct.
This example
On 5/8/25 17:18, Mohamed Mediouni wrote:
Hello,
Just a random email to ask for an account there :)
Done (credentials sent off-list).
On 4/8/25 07:35, Zhao Liu wrote:
Currently, the addressable ID encoding for CPUID[0x1].EBX[bits 16-23]
(Maximum number of addressable IDs for logical processors in this
physical package) is covered by vendor_cpuid_only_v2 compat property.
The previous consideration was to avoid breaking migration
On 4/8/25 15:33, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (11):
hw/sd/sdcard: Do not ignore errors in sd_cmd_to_sendingdata()
hw/sd/sdcard: Factor sd_response_size() out
hw/sd/sdbus: Provide buffer size to sdbus_do_command()
hw/sd/sdcard: Fill SPI response bits in card
On 4/8/25 17:20, Eric Auger wrote:
With a microvm-only build based on a custom device config,
we get a link failure due to undefined reference to
build_pci_host_bridge_osc_method() which is defined in hw/acpi/pci.c and
whose compilation depends on CONFIG_ACPI_PCI. Although CONFIG_ACPI
and CONFIG_
e ramfb romfile compatibility")
Signed-off-by: Cédric Le Goater
---
hw/vfio/pci.c | 3 +++
1 file changed, 3 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
m/system.h
Anyhow,
Reviewed-by: Philippe Mathieu-Daudé
qemu_add_machine_init_done_notifier()
Signed-off-by: Cédric Le Goater
---
hw/arm/virt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index
ef6be3660f5fb38da84235c32dc2d1
On 5/8/25 01:03, Richard Henderson wrote:
On 8/4/25 23:33, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (11):
hw/sd/sdcard: Do not ignore errors in sd_cmd_to_sendingdata()
hw/sd/sdcard: Factor sd_response_size() out
hw/sd/sdbus: Provide buffer size to sdbus_do_command()
hw
On 4/8/25 16:23, Mohamed Mediouni wrote:
Signed-off-by: Mohamed Mediouni
---
accel/hvf/hvf-all.c| 7 +--
hw/arm/virt.c | 41 --
include/hw/boards.h| 4 ++--
include/system/hvf_int.h | 2 ++
target/arm/hvf-stub.c
On 4/8/25 16:23, Mohamed Mediouni wrote:
Windows Hypervisor Platform's vGIC doesn't support ITS.
Deal with this by reporting to the user and not creating the ITS device.
Signed-off-by: Mohamed Mediouni
---
hw/arm/virt.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/arm/v
On 4/8/25 16:23, Mohamed Mediouni wrote:
Signed-off-by: Mohamed Mediouni
---
accel/whpx/whpx-common.c| 1 +
meson.build | 21 +-
target/arm/meson.build | 1 +
target/arm/whpx/meson.build | 3 +
target/arm/whpx/whpx-all.c | 845 ++
On 4/8/25 16:23, Mohamed Mediouni wrote:
This allows edk2 to work, although u-boot is still not functional.
Signed-off-by: Mohamed Mediouni
---
accel/whpx/whpx-common.c | 201 ---
1 file changed, 147 insertions(+), 54 deletions(-)
diff --git a/accel/whpx/
Hi Pierrick,
On 4/8/25 20:39, Pierrick Bouvier wrote:
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
semihosting/arm-compat-semi.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/semihosting/arm-compat-semi.c b/semihosting/a
On 4/8/25 18:12, Mohamed Mediouni wrote:
On 4. Aug 2025, at 18:00, Claudio Fontana wrote:
On 8/4/25 16:23, Mohamed Mediouni wrote:
From: Philippe Mathieu-Daudé
hwaccel_enabled() return whether any hardware accelerator
is available.
Available or enabled?
enabled
Oops indeed
-8372-b62b3bcd0...@codethink.co.uk/
Inspired-by: Guenter Roeck
Inspired-by: Ben Dooks
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
tests/functional/meson.build | 1 +
tests/functional/test_riscv64_sifive_u.py | 51
Unfortunately when adding sd_cmd_to_sendingdata() in commit
f486bf7d109 we neglected to return any possible error. Fix.
Fixes: f486bf7d109 ("hw/sd/sdcard: Introduce sd_cmd_to_sendingdata and
sd_generic_read_byte")
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
nter Roeck
Reported-by: Ben Dooks
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index ee81dc09991..22f30997713 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -1591,9 +1591,20 @@ static sd_
In SPI mode, SWITCH_FUNCTION is valid in all mode
(except the IDLE one).
Fixes: 775616c3ae8 ("Partial SD card SPI mode support")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/sd/sd.c b/hw/sd/
spi_cmd_SEND_CSD() and spi_cmd_SEND_CID() are very
similar. Factor the common code as spi_cmd_SEND_CxD().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index a9efa158594
avoid further bitrot.
Regards,
Phil.
Philippe Mathieu-Daudé (11):
hw/sd/sdcard: Do not ignore errors in sd_cmd_to_sendingdata()
hw/sd/sdcard: Factor sd_response_size() out
hw/sd/sdbus: Provide buffer size to sdbus_do_command()
hw/sd/sdcard: Fill SPI response bits in card code
hw/sd/sdcard
-sd.c.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 32 ---
hw/sd/ssi-sd.c | 87 --
2 files changed, 35 insertions(+), 84 deletions(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 069107a2e70..cbcc180f6a4 100644
--- a/hw/sd
y the size filled
in the buffer. Convert the returned type to unsigned and remove
the few unreachable lines in callers.
This allow to check for possible overflow in sd_do_command().
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sd.h | 23 +--
hw/sd/allw
SD card mode is a superset of its state (SDState::state),
no need to migrate it.
Use sd_mode() to get the SDCardModes from the SDCardStates.
Fixes: 50a5be6c3d5 ("hw/sd.c: add SD card save/load support")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c
While spi_cmd_SEND_OP_COND() is incomplete, sd_cmd_SEND_OP_COND()
is, except it doesn't return the correct value in SPI mode.
Correct and use, removing the need for spi_cmd_SEND_OP_COND().
Fixes: 775616c3ae8 ("Partial SD card SPI mode support")
Signed-off-by: Philippe Mathieu-Da
In SPI mode, R2 is a 2-byte value.
Implement in spi_response_r2_make() and
return SPI R2 in the SEND_STATUS commands.
Reported-by: Guenter Roeck
Fixes: 775616c3ae8 ("Partial SD card SPI mode support")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.
Set @rsplen once before switching to fill the response buffer.
This will allow to assert in a single place that the buffer is
big enough to be filled with the response.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 36 +---
1 file changed, 29 insertions
ame type. The
impact on code size is negligible: qemu-system-x86_64's text segment
grows by 1448 bytes.
Signed-off-by: Markus Armbruster
---
docs/devel/qapi-code-gen.rst | 25
scripts/qapi/commands.py | 44 ----
2 files changed, 19 insertions(+), 50 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 1/8/25 09:19, Richard Henderson wrote:
On 8/1/25 07:27, Philippe Mathieu-Daudé wrote:
@@ -746,6 +761,10 @@ static size_t sd_response_r3_make(SDState *sd,
uint8_t *response, size_t respsz)
{
size_t rsplen = 4;
+ if (sd_is_spi(sd)) {
+ rsplen += sd_response_r1_make(sd
hanged, 23 insertions(+), 22 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
(+), 7 deletions(-)
create mode 100644 tests/functional/avr/meson.build
rename tests/functional/{test_avr_mega2560.py => avr/test_mega2560.py} (100%)
rename tests/functional/{test_avr_uno.py => avr/test_uno.py} (100%)
Reviewed-by: Philippe Mathieu-Daudé
son.build
rename tests/functional/{test_sparc64_migration.py =>
sparc64/test_migration.py} (100%)
rename tests/functional/{test_sparc64_sun4u.py => sparc64/test_sun4u.py}
(100%)
rename tests/functional/{test_sparc64_tuxrun.py => sparc64/test_tuxrun.py}
(100%)
Reviewed-by: Philippe Mathieu-Daudé
r1k')
subdir('ppc')
subdir('ppc64')
-
-test_riscv64_timeouts = {
- 'riscv64_tuxrun' : 120,
-}
+subdir('riscv32')
+subdir('riscv64')
Here again I'd merge in a single 'riscv/' directory. Anyhow,
Reviewed-by: Philippe Mathieu-Daudé
(+), 6 deletions(-)
create mode 100644 tests/functional/or1k/meson.build
rename tests/functional/{test_or1k_replay.py => or1k/test_replay.py} (100%)
rename tests/functional/{test_or1k_sim.py => or1k/test_sim.py} (100%)
Reviewed-by: Philippe Mathieu-Daudé
hppa')
subdir('i386')
+subdir('loongarch64')
I'd just go with generic 'loongarch'. Regardless:
Reviewed-by: Philippe Mathieu-Daudé
ration.py => alpha/test_migration.py}
(100%)
rename tests/functional/{test_alpha_replay.py => alpha/test_replay.py} (100%)
Reviewed-by: Philippe Mathieu-Daudé
ild
rename tests/functional/{test_hppa_seabios.py => hppa/test_seabios.py} (100%)
Reviewed-by: Philippe Mathieu-Daudé
)
rename tests/functional/{test_m68k_tuxrun.py => m68k/test_tuxrun.py} (100%)
Reviewed-by: Philippe Mathieu-Daudé
e tests/functional/{test_s390x_tuxrun.py => s390x/test_tuxrun.py} (100%)
Reviewed-by: Philippe Mathieu-Daudé
(+), 6 deletions(-)
create mode 100644 tests/functional/xtensa/meson.build
rename tests/functional/{test_xtensa_lx60.py => xtensa/test_lx60.py} (100%)
rename tests/functional/{test_xtensa_replay.py => xtensa/test_replay.py}
(100%)
Reviewed-by: Philippe Mathieu-Daudé
st_sh4_timeouts = {
- 'sh4_tuxrun' : 240,
-}
+subdir('sh4')
+subdir('sh4eb')
Here also I'd keep a single sh4/ directory (it is the same architecture
with an endianness variant we're going to remove).
Reviewed-by: Philippe Mathieu-Daudé
gt; rx/test_gdbsim.py} (100%)
Reviewed-by: Philippe Mathieu-Daudé
/test_tuxrun.py}
(100%)
+subdir('mips')
+subdir('mipsel')
+subdir('mips64')
+subdir('mips64el')
Just one single comment here. I'd rather have a single mips/ directory
and keep the variants inside it, i.e.:
tests/functional/mips/test_mips64el_malta.py
Anyhow:
Reviewed-by: Philippe Mathieu-Daudé
[*]. Otherwise,
Reviewed-by: Philippe Mathieu-Daudé
+VFIOPCIDevice *vfio_pci_from_vfio_device(VFIODevice *vbasedev)
+{
+if (vbasedev && vbasedev->type == VFIO_DEVICE_TYPE_PCI) {
+return container_of(vbasedev, VFIOPCIDevice, vbasedev);
+}
+return NULL;
+}
STATE_BOOL(ga_enabled, AMDVIState),
- VMSTATE_BOOL(ats_enabled, AMDVIState),
+ /* bool ats_enabled is obsolete */
+ VMSTATE_UNUSED(1),
VMSTATE_UNUSED(1), /* was ats_enabled */
Otherwise,
Reviewed-by: Philippe Mathieu-Daudé
(Cc'ing few more ppl who worked on hw/sd/)
On 31/7/25 23:27, Philippe Mathieu-Daudé wrote:
This series fix a pair of issues with SD cards used wired
via a SPI link / controller.
Such mode implementation was minimal. I was testing it with
the ARM Gumstix machines, but we remove them i
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