Hi,
On 17/7/25 11:38, Djordje Todorovic wrote:
I addressed several comments in this version, major ones:
- split CPC / CMGCR into separated changes
- split CPS into a separated change
- added functional tests for boston-aia board
Djordje Todorovic (14):
hw/misc: Add RISC-V CMGCR device implementation
hw/misc: Add RISC-V CPC device implementation
hw/riscv: Add support for RISCV CPS
I'm not keen on having theses models duplicated with the
MIPS ones. Are the IPs really different? They are just
dealing with bit masks to stop/start VPs AFAICT.
Could we model them with plain CPUState objects instead?
