[PATCH v2 2/3] hw/arm/stm32f100: Add DMA support for stm32f100

From: Nikita Shubin Add STM32 DMA support for stm32f100 SoC. Signals from periphery to DMA are not connected, as no STM32 periphery currently supports DMA. Signed-off-by: Nikita Shubin --- hw/arm/Kconfig | 1 + hw/arm/stm32f100_soc.c | 51

[PATCH v2 1/3] hw/dma: Add STM32 platfrom DMA controller emulation

From: Nikita Shubin STMicroelectronics STM32 SoCs integrate DMA engine that supports: * Independent concurrent DMA transfers using 7/5 DMA channels * Generation of interrupts on various conditions during execution * PERIPH to MEMORY transactions, invoked by peripheral device models * MEMORY to

[PATCH v2 0/3] Add STM32 DMA model

From: Nikita Shubin Add STM32 DMA model and include it in STM32F100 SoC. The model is fully compatible with GD32F303x DMA. To: qemu-devel@nongnu.org Cc: Paolo Bonzini Cc: Alistair Francis Cc: Peter Maydell Cc: qemu-...@nongnu.org Cc: Alexandre Iooss Cc: Fabiano Rosas Cc: Laurent Vivier

[PATCH v2 3/3] tests/qtest: add qtests for STM32 DMA

From: Nikita Shubin Signed-off-by: Nikita Shubin --- tests/qtest/meson.build | 1 + tests/qtest/stm32-dma-test.c | 421 +++ 2 files changed, 422 insertions(+) create mode 100644 tests/qtest/stm32-dma-test.c diff --git a/tests/qtest/meson.build b/tests

[PATCH PoC 3/7] gpiodev: Add GPIO device frontend

From: Nikita Shubin Add GPIO device front end with helper functions to provide information about GPIO Port to Backends and to allow Frontend to set data. To use it GPIO device should register with qemu_gpio_fe_init() and provide handlers with qemu_gpio_fe_set_handlers(). Notifications about

[PATCH 0/3] Add STM32 DMA model

From: Nikita Shubin Add STM32 DMA model and include it in STM32F100 SoC. The model is fully compatible with GD32F30x DMA. To: qemu-devel@nongnu.org Cc: Paolo Bonzini Cc: Alistair Francis Cc: Peter Maydell Cc: qemu-...@nongnu.org Cc: Alexandre Iooss Cc: Fabiano Rosas Cc: Laurent Vivier Cc

[PATCH 1/3] hw/dma: Add STM32 platfrom DMA controller emulation

From: Nikita Shubin STMicroelectronics STM32 SoCs integrate DMA engine that supports: * Independent concurrent DMA transfers using 7/5 DMA channels * Generation of interrupts on various conditions during execution * PERIPH to MEMORY transactions, invoked by peripheral device models * MEMORY to

[PATCH 3/3] tests/qtest: add qtests for STM32 DMA

From: Nikita Shubin Signed-off-by: Nikita Shubin --- tests/qtest/meson.build | 1 + tests/qtest/stm32-dma-test.c | 415 +++ 2 files changed, 416 insertions(+) create mode 100644 tests/qtest/stm32-dma-test.c diff --git a/tests/qtest/meson.build b/tests

[PATCH 2/3] hw/arm/stm32f100: Add DMA support for stm32f100

From: Nikita Shubin Add STM32 DMA support for stm32f100 SoC. Signals from periphery to DMA are not connected, as no STM32 periphery currently supports DMA. Signed-off-by: Nikita Shubin --- hw/arm/Kconfig | 1 + hw/arm/stm32f100_soc.c | 51

[PATCH PoC 0/7] Interact with QEMU GPIO models via gpiodev

ing we can get from it is monitoring lines set by QEMU guest. So i didn't bother implementing it yet. I prepare a suite with whing nessary if someone wants to test/tinker with current series: Link: git://git.maquefel.me/qemu-gpiodev/qemu-guse-suite.git Signed-off-by: Nikita Shubin --- Nikit

[PATCH PoC 7/7] gpiodev: Add gpiobackend over GUSE

From: Nikita Shubin Add GUSE (FUSE based kernel module similiar to CUSE) based backend. This allows transparent usage of Linux GPIO UAPI based tools like in kernel tools/gpio or libgpiod. libgpiod requires some modification to allow "/sys/class/guse" in gpiod_check_gpiochip_dev

[PATCH PoC 1/7] QAPI: gpio JSON

From: Nikita Shubin Signed-off-by: Nikita Shubin --- qapi/gpio.json| 68 +++ qapi/meson.build | 1 + qapi/qapi-schema.json | 1 + 3 files changed, 70 insertions(+) diff --git a/qapi/gpio.json b/qapi/gpio.json new file mode 100644

[PATCH PoC 4/7] gpiodev: Add GPIO backend over chardev

From: Nikita Shubin Currently based on passing linux GPIO UAPI structs over UNIX socket. This is more a PoC than a real application, still this is something to start with. Signed-off-by: Nikita Shubin --- gpiodev/gpio-chardev.c | 479 + gpiodev

[PATCH PoC 5/7] hw/gpio/aspeed: Add gpiodev support

From: Nikita Shubin Add gpiodev support for: - getting line info - getting/setting lines - monitoring line events - monitoting config events Binding is done via id, i.e.: ... -gpiodev chardev,id=aspeed-gpio0 Signed-off-by: Nikita Shubin --- hw/gpio/aspeed_gpio.c | 127

[PATCH PoC 2/7] Add gpiodev dummy

From: Nikita Shubin Add gpiodev stub with single help option. Signed-off-by: Nikita Shubin --- gpiodev/gpio.c | 145 + gpiodev/meson.build| 5 ++ include/gpiodev/gpio.h | 34 meson.build| 11 +++- qemu

[PATCH PoC 6/7] hw/arm: ast2600: set id for gpio

From: Nikita Shubin Set device id for gpios to allow gpiodev binding. Signed-off-by: Nikita Shubin --- hw/arm/aspeed_ast2600.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 07210483bb29a50824c8312021bebf1ca32cac95

[PATCH v2] hw/char: stm32f2xx_usart: replace print with trace

From: Nikita Shubin Drop debug printing macros and replace them with according trace functions. Signed-off-by: Nikita Shubin --- v1->v2: Phil: - fix typo s/recieve/receive/ - initialize 'retvalue' with zero --- hw/char/stm32f2xx_usart.c | 49 ++-

[PATCH] hw/char: stm32f2xx_usart: replace print with trace

From: Nikita Shubin Drop debug printing macros and replace them with according trace functions. Signed-off-by: Nikita Shubin --- hw/char/stm32f2xx_usart.c | 47 ++- hw/char/trace-events | 6 + 2 files changed, 28 insertions(+), 25 deletions

Re: [PATCH v17 00/16] TCG code quality tracking

ope for another spin ? Especially with graphs, which are missing in latest series. --- Yours, Nikita Shubin

[PATCH] hw/block: m25p80: support RDID_90 for Winbond

From: Nikita Shubin Make Winbond support RDID_90 as all winbond SPI NOR Flashes support Read Manufacturer/Device ID (90h) command. Signed-off-by: Nikita Shubin --- hw/block/m25p80.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index

[PATCH] hw/dma: Add Intel I/OAT DMA controller emulation

From: Nikita Shubin Add a memcpy only model of I/OAT DMA found on some Xeon based motherboards. Signed-off-by: Nikita Shubin --- Changes from RFC: - replaced all read()/write() with pci_dma_read/write() Link: https://patchwork.kernel.org/project/qemu-devel/patch/20240524114547.28801-1

[RFC PATCH] hw/dma: Add Intel I/OAT DMA controller emulation

From: Nikita Shubin Add a memcpy only model of I/OAT DMA found on some Xeon based motherboards. Signed-off-by: Nikita Shubin --- Started as complementary device for a driver that can't get working without any DMA. So it's worth (at least) mentioning it on mail lists. Tested

Re: [RFC PATCH v2 1/2] hw/riscv: hart: replace array access with qemu_get_cpu()

Hello Alistair! On Mon, 2023-09-18 at 11:50 +1000, Alistair Francis wrote: > On Thu, Sep 14, 2023 at 6:09 PM Nikita Shubin > wrote: > > > > From: Nikita Shubin > > > > Replace all RISCVHartArrayState->harts[idx] with > > qemu_get_cpu()/cpu_by_arch_id()

[PATCH] gdbstub: Fix SEGFAULT in find_cpu_clusters()

From: Nikita Shubin target_xml is a dynamic GString, use NULL to initialize it. Fixes: 56e534bd11 ("gdbstub: refactor get_feature_xml") Signed-off-by: Nikita Shubin --- Observed with: build-qemu/qemu-system-riscv64 -M sifive_u -bios none -nographic -s Segmentation fault --- gdbstub

[RFC PATCH v2 1/2] hw/riscv: hart: replace array access with qemu_get_cpu()

From: Nikita Shubin Replace all RISCVHartArrayState->harts[idx] with qemu_get_cpu()/cpu_by_arch_id(). cpu_index is guaranteed to be continuus by cpu_get_free_index(), so they can be accessed in same order they were added. "Hart IDs might not necessarily be numbered contiguou

[RFC PATCH v2 0/2] hw/riscv: hart: allow other cpu instance

From: Nikita Shubin Currently it is not possible to overload instance of RISCVCPU, i.e. something like this: static const TypeInfo riscv_cpu_type_infos[] = { { .name = TYPE_ANOTHER_RISCV_CPU, .parent = TYPE_RISCV_CPU, .instance_size = sizeof(MyCPUState

[RFC PATCH v2 2/2] hw/riscv: hart: allow other cpu instance

From: Nikita Shubin Allow using instances derivative from RISCVCPU Signed-off-by: Nikita Shubin --- hw/riscv/riscv_hart.c | 20 include/hw/riscv/riscv_hart.h | 2 +- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv

[PATCH v3] target/riscv: don't read CSR in riscv_csrrw_do64

From: Nikita Shubin As per ISA: "For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read." trans_csrrwi() and trans_csrrw() call do_csrw() if rd=x0, do_csrw() calls riscv_csrrw_do64(), via h

Re: [RFC PATCH] hw/riscv: hart: allow other cpu instance

Hello Deniel! On Mon, 2023-07-31 at 11:12 -0300, Daniel Henrique Barboza wrote: > > > > > > On 7/27/23 05:05, Nikita Shubin wrote: > > > > From: Nikita Shubin > > > > > > > > Allow using instances derivative from

[PATCH v2] target/riscv: don't read write-only CSR

From: Nikita Shubin In case of write-only CSR don't return illegal inst error when CSR is written and lacks read op. Signed-off-by: Nikita Shubin --- Changelog: - fixed uninitialized old_value Anyway it not might be a good idea to read CSR when we are not asked for, during CSRRW or C

[RFC PATCH] hw/riscv: hart: allow other cpu instance

From: Nikita Shubin Allow using instances derivative from RISCVCPU Signed-off-by: Nikita Shubin --- Currently it is not possible to overload instance of RISCVCPU, i.e. something like this: static const TypeInfo riscv_cpu_type_infos[] = { { .name = TYPE_ANOTHER_RISCV_CPU

[PATCH] target/riscv: don't read write-only CSR

From: Nikita Shubin In case of write-only CSR don't return illegal inst error when CSR is written and lacks read op. Signed-off-by: Nikita Shubin --- Anyway it not might be a good idea to read CSR when we are not asked for, during CSRRW or CSRRWI: "For CSRRWI, if rd=x0, then the i

Re: [PATCH] target/riscv: fix priv enum

Hi Anup! On Thu, 26 May 2022 15:37:54 +0530 Anup Patel wrote: > On Thu, May 26, 2022 at 2:15 PM Nikita Shubin > wrote: > > > > From: Nikita Shubin > > > > Add PRIV_VERSION_UNKNOWN to enum, otherwise PRIV_VERSION_1_10_0 will > > be overwritten to PRIV

[PATCH] target/riscv: fix priv enum

From: Nikita Shubin Add PRIV_VERSION_UNKNOWN to enum, otherwise PRIV_VERSION_1_10_0 will be overwritten to PRIV_VERSION_1_12_0 in riscv_cpu_realize. Fixes: a46d410c5c ("target/riscv: Define simpler privileged spec version numbering") Signed-off-by: Nikita Shubin --- target/riscv

[PATCH] target/riscv/pmp: fix no pmp illegal intrs

From: Nikita Shubin As per the privilege specification, any access from S/U mode should fail if no pmp region is configured and pmp is present, othwerwise access should succeed. Fixes: d102f19a208 (target/riscv/pmp: Raise exception if no PMP entry is configured) Resolves: https://gitlab.com

Re: [PATCH] target/riscv/pmp: fix no pmp illegal intrs

Hello Richard! On Tue, 14 Dec 2021 13:13:57 -0800 Richard Henderson wrote: > On 12/14/21 1:12 PM, Richard Henderson wrote: > > On 12/14/21 1:26 AM, Nikita Shubin wrote: > >> -    if (!pmp_get_num_rules(env) && (prev_priv != PRV_M)) { > >> +    if (r

[PATCH] target/riscv/pmp: fix no pmp illegal intrs

From: Nikita Shubin As per the privilege specification, any access from S/U mode should fail if no pmp region is configured and pmp is present, othwerwise access should succeed. Fixes: d102f19a208 (target/riscv/pmp: Raise exception if no PMP entry is configured) Signed-off-by: Nikita Shubin