On 8.6.19. 07:32, Aleksandar Markovic wrote:
On Jun 6, 2019 3:49 PM, "Mateja Marjanovic"
mailto:mateja.marjano...@rt-rk.com>> wrote:
>
> From: Mateja Marjanovic <mailto:mateja.marjano...@rt-rk.com>>
>
> Add support for DSPRAM (Data Scratch Pad RAM). It
From: Mateja Marjanovic
This patch is a merge of Yongbok Kim's DSPRAM implementation
with the upstream, with some of Philippe Mathieu-Daude's comments.
It still needs some fixing (work in progress).
Mateja Marjanovic (1):
target/mips: Add implementation of DSPRAM
default-co
From: Mateja Marjanovic
Add support for DSPRAM (Data Scratch Pad RAM). It still needs
some minor fixing, but the structure is right.
Signed-off-by: Mateja Marjanovic
---
default-configs/mips-softmmu-common.mak | 1 +
hw/mips/cps.c | 28 +-
hw/misc
Mateja Marjanovic writes:
From: Mateja Marjanovic
Eliminate loops for better performance.
Have you done any measurements of the bellow loop unrolling? Because
this is something that maybe we can achieve and let the compiler make
the choice.
I know that Mateja did extensive performance
On 2.6.19. 09:06, Aleksandar Markovic wrote:
On Jun 1, 2019 4:16 PM, "Aleksandar Markovic" <mailto:amarko...@wavecomp.com>> wrote:
>
> > From: Mateja Marjanovic <mailto:mateja.marjano...@rt-rk.com>>
> > Sent: Monday, March 4, 2019 5:51 PM
>
On 20.5.19. 14:59, Aleksandar Markovic wrote:
On Apr 2, 2019 3:47 PM, "Mateja Marjanovic"
mailto:mateja.marjano...@rt-rk.com>> wrote:
>
> From: Mateja Marjanovic <mailto:mateja.marjano...@rt-rk.com>>
>
> Fix the case when the host is a big endian mach
On 19.5.19. 07:25, Aleksandar Markovic wrote:
On Apr 2, 2019 3:49 PM, "Mateja Marjanovic"
mailto:mateja.marjano...@rt-rk.com>> wrote:
>
> From: Mateja Marjanovic <mailto:mateja.marjano...@rt-rk.com>>
>
> The old version of the helper for the INSERT.
From: Mateja Marjanovic
Optimize ILVR. instructions, using
directly tcg registers and logic performed on
them, and instead of shifting the bit mask or
assigning a new tcg constant to the bit mask,
assign a new (shifted) uint64_t value to the
bit mask.
Performance measurement is done by
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV., using
directly tcg registers and performing logic on them
instead of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance
after converting from helpers
From: Mateja Marjanovic
Optimize and refactor MSA instructions ILVEV.,
ILVOD., ILVL. and ILVR..
v9:
- Tests were changed, instead of iterating through the
loop 10 million times and calling the instruction
once, iterate through the loop 1 million times, and
call the instruction ten
From: Mateja Marjanovic
Optimize ILVL. instructions, using
directly tcg registers and logic performed on
them, and instead of shifting the bit mask or
assigning a new tcg constant to the bit mask,
assign a new (shifted) uint64_t value to the
bit mask.
Performance measurement is done by
From: Mateja Marjanovic
Optimize set of MSA instructions ILVOD., using
directly tcg registers and performing logic on them instead
of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance
after converting from helpers
From: Mateja Marjanovic
The implementation for ILVEV.D and ILVR.D instructions
is equivalent, so use a single handler for both of them.
Suggested-by: Aleksandar Markovic
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 29 +++--
1 file changed, 11
From: Mateja Marjanovic
The implementation for ILVOD.D and ILVL.D instructions
is equivalent, so use a single handler for both of them.
Suggested-by: Aleksandar Markovic
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 27 ++-
1 file changed, 10
From: Mateja Marjanovic
The implementation for ILVEV.D and ILVR.D instructions
is equivalent, so use a single handler for both of them.
Suggested-by: Aleksandar Markovic
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 30 +++---
1 file changed, 11
From: Mateja Marjanovic
Optimize ILVR. instructions, using a hybrid
approach. For byte data elements, use a helper with an
unrolled loop (having much better performance than
direct tcg translation), for halfword, word and
doubleword data elements use directly tcg registers
and logic performed on
From: Mateja Marjanovic
The implementation for ILVOD.D and ILVL.D instructions
is equivalent, so use a single handler for both of them.
Suggested-by: Aleksandar Markovic
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 27 ++-
1 file changed, 10
From: Mateja Marjanovic
Optimize and refactor MSA instructions ILVEV.,
ILVOD., ILVL. and ILVR..
v8:
- Rebased onto current master branch.
- Inserted Reviewed-by in the applicable commit message.
v7:
- Use tcg constants, instead of uint64_t constants in
ILVEV. and ILVOD. instructions
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV., using
directly tcg registers and performing logic on them
instead of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance
after converting from helpers
From: Mateja Marjanovic
Optimize ILVL. instructions, using a hybrid
approach. For byte data elements, use a helper with an
unrolled loop (having much better performance than
direct tcg translation), for halfword, word and
doubleword data elements use directly tcg registers
and logic performed on
From: Mateja Marjanovic
Optimize set of MSA instructions ILVOD., using
directly tcg registers and performing logic on them instead
of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance
after converting from helpers
On 17.4.19. 22:22, Aleksandar Markovic wrote:
From: Aleksandar Markovic
Subject: Re: [PATCH] target/mips: Amend tests for MSA binary integer operations
From: Mateja Marjanovic
Subject: [PATCH] target/mips: Amend tests for MSA binary integer operations
Amend tests for certain MSA binary
On 17.4.19. 18:41, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH] target/mips: Amend tests for MSA binary integer operations
Amend tests for certain MSA binary integer instructions
(for example DIV_S.B) by appending two missing test cases
to complete standard battery of
>From 55e222d8139e3dd034069fb512b83fd2541ec067 Mon Sep 17 00:00:00 2001
From: Mateja Marjanovic
Date: Wed, 17 Apr 2019 14:50:55 +0200
Subject: [PATCH v7 5/6] target/mips: Merge implementation of ILVEV.D and ILVR.D
The implementation for ILVEV.D and ILVR.D instructions
is equivalent, so us
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV., using
directly tcg registers and performing logic on them
instead of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance
after converting from helpers
From: Mateja Marjanovic
The implementation for ILVOD.D and ILVL.D instructions
is equivalent, so use a single handler for both of them.
Suggested-by: Aleksandar Markovic
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 27 ++-
1 file changed, 10
From: Mateja Marjanovic
Optimize ILVR. instructions, using a hybrid
approach. For byte data elements, use a helper with an
unrolled loop (having much better performance than
direct tcg translation), for halfword, word and
doubleword data elements use directly tcg registers
and logic performed on
From: Mateja Marjanovic
Optimize and refactor MSA instructions ILVEV.,
ILVOD., ILVL. and ILVR..
v7:
- Use tcg constants, instead of uint64_t constants in
ILVEV. and ILVOD. instructions.
- Refactor gen_ilvod_b and gen_ilvod_h functions. Use
the shared function gen_ilvod_bh, which has two
From: Mateja Marjanovic
Optimize ILVL. instructions, using a hybrid
approach. For byte data elements, use a helper with an
unrolled loop (having much better performance than
direct tcg translation), for halfword, word and
doubleword data elements use directly tcg registers
and logic performed on
From: Mateja Marjanovic
Optimize set of MSA instructions ILVOD., using
directly tcg registers and performing logic on them instead
of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance
after converting from helpers
Hello Philippe,
Sorry for replying you so late.
On 4.4.19. 15:42, Philippe Mathieu-Daudé wrote:
Hi Mateja,
On 4/4/19 3:14 PM, Mateja Marjanovic wrote:
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV., using
directly tcg registers and performing logic on them
instead of using
On 16.4.19. 23:20, Aleksandar Markovic wrote:
From: Mateja Marjanovic
+void helper_msa_ilvr_b(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+wr_t *pws = &(env->active_fpu.fpr[ws].wr);
On 13.4.19. 18:05, Aleksandar Markovic wrote:
On Thu, Apr 4, 2019 at 3:18 PM Mateja Marjanovic
wrote:
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV., using
directly tcg registers and performing logic on them
instead of using helpers.
In the following table, the first
On 13.4.19. 18:05, Aleksandar Markovic wrote:
On Thu, Apr 4, 2019 at 3:16 PM Mateja Marjanovic
wrote:
From: Mateja Marjanovic
Optimized ILVR. instructions, using a hybrid
Optimized -> Optimize
approach. For byte data elements, use a helper with an
unrolled loop (much better performa
From: Mateja Marjanovic
Optimize MSA instructions ILVEV., ILVOD.,
ILVL. and ILVR. using the hybrid approach,
MSA helpers in some cases and directly tcg registers in other
cases, so the performance would be better.
v6:
- Add ILVL. and ILVR. MSA instructions
with mixed approaches (with
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV., using
directly tcg registers and performing logic on them
instead of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance,
after converting from
From: Mateja Marjanovic
Optimize set of MSA instructions ILVOD., using
directly tcg registers and performing logic on them instead
of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance,
after converting from
From: Mateja Marjanovic
Optimized ILVL. instructions, using a hybrid
approach. For byte data elements, use a helper with an
unrolled loop (much better performance), for halfword,
word and doubleword data elements use directly tcg
registers and logic performed on them.
Performance measurement is
From: Mateja Marjanovic
Optimized ILVR. instructions, using a hybrid
approach. For byte data elements, use a helper with an
unrolled loop (much better performance), for halfword,
word and doubleword data elements use directly tcg
registers and logic performed on them.
Performance measurement is
On 3.4.19. 01:25, Aleksandar Markovic wrote:
On Apr 2, 2019 5:20 PM, "Mateja Marjanovic"
mailto:mateja.marjano...@rt-rk.com>> wrote:
>
> From: Mateja Marjanovic <mailto:mateja.marjano...@rt-rk.com>>
>
> Optimize set of MSA instructions ILVEV, using
On 2.4.19. 22:50, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v4 5/5] target/mips: Refactor and fix INSERT.
instructions
From: Mateja Marjanovic
The old version of the helper for the INSERT. MSA instructions
has been replaced with four helpers that don't use s
On 2.4.19. 20:51, Aleksandar Markovic wrote:
+/*
+ * [MSA] ILVEV.D wd, ws, wt
+ *
+ * Vector Interleave Even (Double data elements)
+ *
+ */
Double -> Doubleword
I will change it in v6.
On 2.4.19. 20:37, Philippe Mathieu-Daudé wrote:
On 4/2/19 7:07 PM, Aleksandar Markovic wrote:
From: Philippe Mathieu-Daudé
Subject: Re: [Qemu-devel] [PATCH v5 2/2] target/mips: Optimize ILVEV.
MSA instructions
Hi Mateja,
On 4/2/19 5:15 PM, Mateja Marjanovic wrote:
From: Mateja Marjanovic
On 2.4.19. 17:08, Philippe Mathieu-Daudé wrote:
Hi Mateja,
On 4/2/19 2:11 PM, Mateja Marjanovic wrote:
From: Mateja Marjanovic
MSA instructions DIV_. when dividing by zero,
didn't return the same value when executed on a referent hardware
(FPGA MIPS 64 r6, little endian) and when exe
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV, using directly
tcg registers and performing logic on them instead of
using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance,
after converting from helpers
From: Mateja Marjanovic
Optimize MSA instructions ILVEV. and ILVOD.,
using directly tcg registers and performing logic on
them insted of using helpers.
v5:
- Use tcg_gen_deposit function.
- Added performance number for no-deposit and
with-deposit cases of ILVEV.W.
- Minor changes in
From: Mateja Marjanovic
Optimize set of MSA instructions ILVOD, using directly
tcg registers and performing logic on them instead of
using helpers.
instr|| before|| after
==
ilvod.b || 117.50 ms || 24.99 ms
ilvod.h || 93.16 ms || 24.27
From: Mateja Marjanovic
The old version of the helper for the INSERT. MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic
---
target/mips/hel
From: Mateja Marjanovic
Fix the case when the host is a big endian machine, and change
the approach toward ST. instruction helpers.
Signed-off-by: Mateja Marjanovic
---
target/mips/op_helper.c | 188 ++--
1 file changed, 168 insertions(+), 20
From: Mateja Marjanovic
Fix support for MSA instructions while executing QEMU on a
machine that uses big endian MIPS CPU. This is achieved by
changing the implementation of helpers for MSA instructions
ST., LD., INSERT. (and D on MIPS64),
COPY_S. (and D on MIPS64) and COPY_U. (and W
on MIPS64
From: Mateja Marjanovic
The old version of the helper for the COPY_S. MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic
---
target/mips/hel
From: Mateja Marjanovic
The old version of the helper for the COPY_U. MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic
---
target/mips/hel
From: Mateja Marjanovic
Fix the case when the host is a big endian machine, and change
the approach toward LD. instruction helpers.
Signed-off-by: Mateja Marjanovic
---
target/mips/op_helper.c | 188 ++--
1 file changed, 168 insertions(+), 20
From: Mateja Marjanovic
MSA instructions MOD_. when dividing by zero,
didn't return the same value when executed on a referent hardware
(FPGA MIPS 64 r6, little endian) and when executed on QEMU, which
is not a real bug, because the result when dividing by zero is
UNPREDICTABLE [1] (pag
From: Mateja Marjanovic
MSA instructions DIV_. when dividing by zero,
didn't return the same value when executed on a referent hardware
(FPGA MIPS 64 r6, little endian) and when executed on QEMU, which
is not a real bug, because the result when dividing by zero is
UNPREDICTABLE [1] (pag
From: Mateja Marjanovic
The behaviour when executing DIV_. and MOD_.
differs on a referent hardware (FPGA MIPS 64 r6, little endian) and on
QEMU, when the divisor is equal to zero. That is not a real bug, because
the behaviour in that case is unpredictable (references in commit
messages).
v2
On 1.4.19. 20:02, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v3 4/5] target/mips: Different approach toward COPY_U MSA
instr. and big endian fix
From: Mateja Marjanovic
"Different approach toward..." -> "Refactor and fix COPY_U. instructions&quo
On 1.4.19. 19:58, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v3 2/5] target/mips: MSA instructions st, big endian host fix
From: Mateja Marjanovic
Fix the case when the host is running on a big endian machine,
and change the approach toward st instruction helpers
On 1.4.19. 20:01, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v3 3/5] target/mips: Different approach toward COPY_S MSA
instr. and big endian fix
"Different approach toward..." -> "Refactor and fix COPY_S.
instructions"
I will change that
On 1.4.19. 20:03, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v3 5/5] target/mips: Different approach toward INSERT MSA
instr. and big endian fix
"Different approach toward..." -> "Refactor and fix INSERT.
instructions"
Same goes for this
On 1.4.19. 19:56, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v3 1/5] target/mips: MSA instructions ld, big endian host fix
Start the title with the imperative, such as "target/mips: Fix..."
Use full instruction names, as explained in previous reviews.
On 1.4.19. 19:28, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH 1/2] target/mips: DIV_. MSA insturctions fixed
"insturctions" -> "instructions". Try to find a spell checking tool that will
help
you avoid such cases in the future, especially sin
On 1.4.19. 19:43, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH 0/2] target/mips: Integer division by zero in MSA insturctions
The title look incomplete and uninformative: it mentions "the division by zero"
- but what is done in this case? Is this an impleme
On 1.4.19. 19:30, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH 2/2] target/mips: MOD_. MSA insturctions fixed
From: Mateja Marjanovic
In case of dividing integers by zero, the result is unpredictable [1],
but according to the hardware, the result is not zero, but the
On 1.4.19. 19:53, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v3 0/5] Add support for MSA instructions on a big endian host
"Add" -> "Fix"
Big endian host support should have worked from the moment MSA
support is added to QEMU.
I will change it
From: Mateja Marjanovic
Integer division by zero in MSA insturctions results in unpredictable
behaviour, but according to the hardware, it depends on the sign of
the dividend, or always returns the same value.
Mateja Marjanovic (2):
target/mips: DIV_. MSA insturctions fixed
target/mips
From: Mateja Marjanovic
In case of dividing integers by zero, the result is unpredictable [1],
but according to the hardware, the result is 1 or -1, depending on
the sign of the dividend.
[1] MIPS® Architecture for Programmers
Volume IV-j: The MIPS64® SIMD
Architecture Module, Revision
From: Mateja Marjanovic
In case of dividing integers by zero, the result is unpredictable [1],
but according to the hardware, the result is not zero, but the dividend.
[1] MIPS® Architecture for Programmers
Volume IV-j: The MIPS64® SIMD
Architecture Module, Revision 1.12
Signed-off-by
From: Mateja Marjanovic
The old version of the helper for the INSERT. MSA instructions
has been replaced with a four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic
---
target/mips/hel
From: Mateja Marjanovic
Fix the case when the host is running on a big endian machine,
and change the approach toward ld instruction helpers.
Signed-off-by: Mateja Marjanovic
---
target/mips/op_helper.c | 188 ++--
1 file changed, 168 insertions
From: Mateja Marjanovic
The old version of the helper for the COPY_S. MSA instructions
has been replaced with a four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic
---
target/mips/hel
From: Mateja Marjanovic
The old version of the helper for the COPY_U. MSA instructions
has been replaced with a four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic
---
target/mips/hel
From: Mateja Marjanovic
Fix the case when the host is running on a big endian machine,
and change the approach toward st instruction helpers.
Signed-off-by: Mateja Marjanovic
---
target/mips/op_helper.c | 188 ++--
1 file changed, 168 insertions
From: Mateja Marjanovic
Add support for MSA instructions while executing QEMU on a
machine that uses big endian MIPS CPU. Also change the
implementation of helpers for MSA instructions
ST., LD., INSERT. (and D on MIPS64),
COPY_S. (and D on MIPS64) and COPY_U. (and W
on MIPS64). Instead of using
On 25.3.19. 22:33, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v2 0/7] target/mips: Add support for MSA instructions on a big
endian host
From: Mateja Marjanovic
While working on adding support for big endian hosts on QEMU for the
MSA instructions copy_u, copy_s and
On 25.3.19. 22:16, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Sent: Monday, March 25, 2019 3:52 PM
To: qemu-devel@nongnu.org
Cc: aurel...@aurel32.net; Aleksandar Markovic; Aleksandar Rikalo
Subject: [PATCH v2 5/7] target/mips: Eliminate unreachable case for MSA
instructions copy_u
On 25.3.19. 22:21, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v2 1/7] target/mips: Fix . MSA instructions for
MIPS big endian host
Please split this patch into one for load instructions and another for
store instructions.
I will do that.
I don't think the var
From: Mateja Marjanovic
The copy_u instruction doesn't support doublewords, and supports
words only if the CPU is MIPS64 [1] (page 138), for MIPS32 it
supports only byte and halfword [2] (page 138).
[1] MIPS Architecture for Programmers
Volume IV-j: The MIPS64 SIMD
Architecture M
From: Mateja Marjanovic
Unsigned element copy from MSA registers to GPR when
executed on a MIPS big endian CPU, didn't pick the
right element, and was behaving like on little endian.
Signed-off-by: Mateja Marjanovic
---
target/mips/msa_helper.c | 7 +++
1 file changed, 7 inser
From: Mateja Marjanovic
The fill instruction doesn't support doublewords for
MIPS32 [2] (page 178), but MIPS64 supports doubleword [1] (page 179).
[1] MIPS Architecture for Programmers
Volume IV-j: The MIPS64 SIMD
Architecture Module
[2] MIPS Architecture for Programmers
Volume
From: Mateja Marjanovic
The insert instruction doesn't support doublewords for
MIPS32 [2] (page 223), but MIPS64 supports doubleword [1] (page 224).
[1] MIPS Architecture for Programmers
Volume IV-j: The MIPS64 SIMD
Architecture Module
[2] MIPS Architecture for Programmers
Volu
From: Mateja Marjanovic
While working on adding support for big endian hosts on QEMU for the
MSA instructions copy_u, copy_s and insert, I noticed there was some
unreachable code (copy_u.d doesn't exist), and some unnecessary code
(for instance, insert supports doublewords only on MIPS64
From: Mateja Marjanovic
Inserting from GPR to an element in a MSA register when
executed on a MIPS big endian CPU, didn't pick the
right element, and was behaving like on little endian.
Signed-off-by: Mateja Marjanovic
---
target/mips/msa_helper.c | 7 +++
1 file changed, 7 inser
From: Mateja Marjanovic
Signed element copy from MSA registers to GPR when
executed on a MIPS big endian CPU, didn't pick the
right element, and was behaving like on little endian.
Signed-off-by: Mateja Marjanovic
---
target/mips/msa_helper.c | 7 +++
1 file changed, 7 insertions(+)
From: Mateja Marjanovic
Load and store MSA instructions when executed on a MIPS
big endian CPU, didn't change the endianness, and were
behaving like on little endian.
Signed-off-by: Mateja Marjanovic
---
target/mips/op_helper.c | 79 ++---
1
On 22.3.19. 18:45, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH 2/4] target/mips: Fix copy_s. for MIPS big endian host
From: Mateja Marjanovic
Signed element copy from MSA registers to GPR when
executed on a MIPS big endian CPU, didn't pick the
right element, an
On 22.3.19. 19:04, Aleksandar Markovic wrote:
@@ -1511,9 +1518,11 @@ void helper_msa_insert_df(CPUMIPSState *env, uint32_t
df, uint32_t wd,
case DF_WORD:
pwd->w[n] = (int32_t)rs;
break;
+#ifdef TARGET_MIPS64
case DF_DOUBLE:
pwd->d[n] = (int64_t)rs
On 22.3.19. 18:16, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH 4/4] target/mips: Fix insert. for MIPS big endian host
From: Mateja Marjanovic
Inserting from GPR to an element in a MSA register when
executed on a MIPS big endian CPU, didn't pick the
right element
From: Mateja Marjanovic
Unsigned element copy from MSA registers to GPR when
executed on a MIPS big endian CPU, didn't pick the
right element, and was behaving like on little endian.
Signed-off-by: Mateja Marjanovic
---
target/mips/msa_helper.c | 7 +++
1 file changed, 7 inser
From: Mateja Marjanovic
Inserting from GPR to an element in a MSA register when
executed on a MIPS big endian CPU, didn't pick the
right element, and was behaving like on little endian.
Signed-off-by: Mateja Marjanovic
---
target/mips/msa_helper.c | 9 +
1 file changed, 9 inser
From: Mateja Marjanovic
Signed element copy from MSA registers to GPR when
executed on a MIPS big endian CPU, didn't pick the
right element, and was behaving like on little endian.
Signed-off-by: Mateja Marjanovic
---
target/mips/msa_helper.c | 7 +++
1 file changed, 7 insertions(+)
From: Mateja Marjanovic
Load and store MSA instructions when executed on a MIPS
big endian CPU, didn't change the endianness, and were
behaving like on little endian.
Signed-off-by: Mateja Marjanovic
---
target/mips/op_helper.c | 79 ++---
1
From: Mateja Marjanovic
Change endianness when the host machine has a big endian CPU, for
MSA instructions ., copy_., insert..
Mateja Marjanovic (4):
target/mips: Fix . MSA instructions for MIPS big
endian host
target/mips: Fix copy_s. for MIPS big endian host
target/mips: Fix copy_u
On 19.3.19. 23:02, Alex Bennée wrote:
Aleksandar Markovic writes:
From: Peter Maydell
Subject: Re: [PATCH v3] target/mips: Fix minor bug in FPU
On Tue, 19 Mar 2019 at 19:21, Aleksandar Markovic
wrote:
From: Mateja Marjanovic
Subject: [PATCH v3] target/mips: Fix minor bug in FPU
From
On 19.3.19. 16:27, Peter Maydell wrote:
On Tue, 19 Mar 2019 at 15:22, Mateja Marjanovic
wrote:
From: Mateja Marjanovic
Wrong type of NaN was generated for IEEE 754-2008 by MADDF. and
MSUBF. instructions when the arguments were (inf, zero, nan) or
(zero, inf, nan).
These instructions were
From: Mateja Marjanovic
Eliminate loops for better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/msa_helper.c | 43 ++-
1 file changed, 30 insertions(+), 13 deletions(-)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
From: Mateja Marjanovic
Wrong type of NaN was generated for IEEE 754-2008 by MADDF. and
MSUBF. instructions when the arguments were (inf, zero, nan) or
(zero, inf, nan).
These instructions were tested and the results match with the results
of the machine that has a MIPS64 r6 cpu.
Signed-off-by
From: Mateja Marjanovic
The if-else statement indicates if the system conforms to
IEEE 754-1985 or IEEE 754-2008, and it has different
behaviour depending on that.
v3:
- In case of IEEE 754-1985, return the default-NaN and raise
floating point exception 'Invalid Operation' [1](pag
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV, using directly
tcg registers and performing logic on them instead of
using helpers.
instr|| before|| after
==
ilvev.b || 126.92 ms || 26.41 ms
ilvev.h || 93.67 ms || 25.79
From: Mateja Marjanovic
Optimize MSA instructions ILVEV. and ILVOD.,
using directly tcg registers and performing logic on
them insted of using helpers. Reduce the number of logic
operations to a minimum, add comments and clean up
some typing errors.
Mateja Marjanovic (2):
target/mips
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