From: Mateja Marjanovic <mateja.marjano...@rt-rk.com>
Inserting from GPR to an element in a MSA register when
executed on a MIPS big endian CPU, didn't pick the
right element, and was behaving like on little endian.
Signed-off-by: Mateja Marjanovic <mateja.marjano...@rt-rk.com>
---
target/mips/msa_helper.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 8caf186..0049191 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1500,6 +1500,13 @@ void helper_msa_insert_df(CPUMIPSState *env, uint32_t
df, uint32_t wd,
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
target_ulong rs = env->active_tc.gpr[rs_num];
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < DF_ELEMENTS(df) / 2) {
+ n = DF_ELEMENTS(df) / 2 - n - 1;
+ } else {
+ n = 3 * DF_ELEMENTS(df) / 2 - n - 1;
+ }
+#endif
switch (df) {
case DF_BYTE:
@@ -1511,9 +1518,11 @@ void helper_msa_insert_df(CPUMIPSState *env, uint32_t
df, uint32_t wd,
case DF_WORD:
pwd->w[n] = (int32_t)rs;
break;
+#ifdef TARGET_MIPS64
case DF_DOUBLE:
pwd->d[n] = (int64_t)rs;
break;
+#endif
default:
assert(0);
}
--
2.7.4
