Re: [PATCH v5 6/6] target/ppc: add vmsumudm vmsumcud instructions

> On Jul 24, 2020, at 1:46 PM, Lijun Pan wrote: > > > >> On Jul 24, 2020, at 1:00 PM, Richard Henderson > <mailto:richard.hender...@linaro.org>> wrote: >> >> On 7/23/20 9:58 PM, Lijun Pan wrote: >>> vmsumudm (Power ISA 3.0) - Vector

Re: [PATCH v5 6/6] target/ppc: add vmsumudm vmsumcud instructions

> On Jul 24, 2020, at 1:00 PM, Richard Henderson > wrote: > > On 7/23/20 9:58 PM, Lijun Pan wrote: >> vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo >> VA-form. >> vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-

[PATCH v5 3/6] target/ppc: add vmulh{su}w instructions

vmulhsw: Vector Multiply High Signed Word vmulhuw: Vector Multiply High Unsigned Word Signed-off-by: Lijun Pan --- v4/v5: no change Reviewed-by: Richard Henderson v3: inline the helper_vmulh{su}w multiply directly instead of using macro v2: fix coding style use Power ISA 3.1 flag target

[PATCH v5 2/6] target/ppc: add vmulld to INDEX_op_mul_vec case

Group vmuluwm and vmulld. Make vmulld-specific changes since it belongs to new ISA 3.1. Signed-off-by: Lijun Pan --- v5: no change v4: add missing changes, and split to 5/11, 6/11, 7/11 v3: use tcg_gen_gvec_mul() v2: fix coding style use Power ISA 3.1 flag tcg/ppc/tcg-target.h | 2

[PATCH v5 5/6] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions

Doubleword Signed-off-by: Lijun Pan --- v5: no change v4: add a comment on undefined result of divide operation. fix if(){} coding style issue, remove blank line. v3: add missing divided-by-zero, divided-by-(-1) handling v2: fix coding style use Power ISA 3.1 flag target/ppc/helper.h

[PATCH v5 4/6] target/ppc: add vmulh{su}d instructions

vmulhsd: Vector Multiply High Signed Doubleword vmulhud: Vector Multiply High Unsigned Doubleword Signed-off-by: Lijun Pan --- v4/v5: no change Reviewed-by: Richard Henderson v3: simplify helper_vmulh{su}d v2: fix coding style use Power ISA 3.1 flag target/ppc/helper.h

[PATCH v5 6/6] target/ppc: add vmsumudm vmsumcud instructions

vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo VA-form. vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned Doubleword VA-form. Signed-off-by: Lijun Pan --- v5: update instruction flag for vmsumcud. integrate into this isa3.1 patch serie

[PATCH v5 1/6] Update PowerPC AT_HWCAP2 definition

Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions. Signed-off-by: Lijun Pan --- v5: match the definition with that in linux's arch/powerpc/include/uapi/asm/cputable.h v4: add missing changes, and split to 5/11, 6/11, 7/11 v3: use tcg_gen_gvec_mul() v2: fix coding style

[PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions

, and 9/11 of v4 was accepted by Lauren Vivier. This v5 version updates PPC_FEATURE2_ARCH_3_10 definition in 6/11 of v4, rebases 7/11 8/11 10/11 11/11 of v4, and integrates vmsumudm/vmsumcud patch. Lijun Pan (6): Update PowerPC AT_HWCAP2 definition target/ppc: add vmulld to INDEX_op_mul_vec

Re: [PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition

> On Jul 13, 2020, at 6:47 PM, David Gibson wrote: > > On Mon, Jul 13, 2020 at 02:20:20PM -0500, Lijun Pan wrote: >> >> >>> On Jul 13, 2020, at 12:14 AM, David Gibson >>> wrote: >>> >>> On Wed, Jul 01, 2020 at 06:43:41PM -0500,

Re: [PATCH v4 07/11] target/ppc: add vmulld to INDEX_op_mul_vec case

> On Jul 1, 2020, at 6:43 PM, Lijun Pan wrote: > > Group vmuluwm and vmulld. Make vmulld-specific > changes since it belongs to new ISA 3.1. > > Signed-off-by: Lijun Pan > --- > v4: add missing changes, and split to 5/11, 6/11, 7/11 > v3: use tcg_gen_gvec_m

Re: [PATCH v4 11/11] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions

> On Jul 1, 2020, at 6:47 PM, Lijun Pan wrote: > > vdivsw: Vector Divide Signed Word > vdivuw: Vector Divide Unsigned Word > vdivsd: Vector Divide Signed Doubleword > vdivud: Vector Divide Unsigned Doubleword > vmodsw: Vector Modulo Signed Word > vmoduw: Vector Modul

Re: [PATCH v4 10/11] target/ppc: add vmulh{su}d instructions

> On Jul 1, 2020, at 6:47 PM, Lijun Pan wrote: > > vmulhsd: Vector Multiply High Signed Doubleword > vmulhud: Vector Multiply High Unsigned Doubleword > > Signed-off-by: Lijun Pan > --- > Reviewed-by: Richard Henderson > v3: simplify helper_vmulh{su}d > v2: f

Re: [PATCH v4 08/11] target/ppc: add vmulh{su}w instructions

> On Jul 1, 2020, at 6:43 PM, Lijun Pan wrote: > > vmulhsw: Vector Multiply High Signed Word > vmulhuw: Vector Multiply High Unsigned Word > > Signed-off-by: Lijun Pan > --- > Reviewed-by: Richard Henderson > v3: inline the helper_vmulh{su}w multiply directly

Re: [PATCH v3] target/ppc: add vmsumudm vmsumcud instructions

> On Jul 6, 2020, at 2:53 AM, David Gibson wrote: > > On Mon, Jun 22, 2020 at 11:25:01PM -0500, Lijun Pan wrote: >> vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo >> VA-form. >> vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write C

Re: [PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition

> On Jul 13, 2020, at 12:14 AM, David Gibson > wrote: > > On Wed, Jul 01, 2020 at 06:43:41PM -0500, Lijun Pan wrote: >> Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions. >> >> Signed-off-by: Lijun Pan >> --- >> v4: add missing ch

[PATCH v4 10/11] target/ppc: add vmulh{su}d instructions

vmulhsd: Vector Multiply High Signed Doubleword vmulhud: Vector Multiply High Unsigned Doubleword Signed-off-by: Lijun Pan --- Reviewed-by: Richard Henderson v3: simplify helper_vmulh{su}d v2: fix coding style use Power ISA 3.1 flag target/ppc/helper.h | 2 ++ target/ppc

[PATCH v4 11/11] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions

Doubleword Signed-off-by: Lijun Pan --- v4: add a comment on undefined result of divide operation. fix if(){} coding style issue, remove blank line. v3: add missing divided-by-zero, divided-by-(-1) handling v2: fix coding style use Power ISA 3.1 flag target/ppc/helper.h | 8

[PATCH v4 05/11] target/ppc: add vmulld instruction

vmulld: Vector Multiply Low Doubleword. Signed-off-by: Lijun Pan --- v4: add missing changes, and split to 5/11, 6/11, 7/11 v3: use tcg_gen_gvec_mul() v2: fix coding style use Power ISA 3.1 flag target/ppc/translate/vmx-impl.inc.c | 1 + target/ppc/translate/vmx-ops.inc.c | 4 2

[PATCH v4 03/11] target/ppc: add byte-reverse br[dwh] instructions

POWER ISA 3.1 introduces following byte-reverse instructions: brd: Byte-Reverse Doubleword X-form brw: Byte-Reverse Word X-form brh: Byte-Reverse Halfword X-form Signed-off-by: Lijun Pan --- v4: make it compile on all targets v3: fix the store issue in br[dwh] simplify brw implementation

[PATCH v4 09/11] fix the prototype of muls64/mulu64

The prototypes of muls64/mulu64 in host-utils.h should match the definitions in host-utils.c Signed-off-by: Lijun Pan --- Reviewed-by: Richard Henderson no change since v1 include/qemu/host-utils.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/qemu/host

[PATCH v4 04/11] target/ppc: convert vmuluwm to tcg_gen_gvec_mul

Convert the original implementation of vmuluwm to the more generic tcg_gen_gvec_mul. Signed-off-by: Lijun Pan --- Reviewed-by: Richard Henderson v3: newly introduced target/ppc/helper.h | 1 - target/ppc/int_helper.c | 13 - target/ppc/translate/vmx

[PATCH v4 07/11] target/ppc: add vmulld to INDEX_op_mul_vec case

Group vmuluwm and vmulld. Make vmulld-specific changes since it belongs to new ISA 3.1. Signed-off-by: Lijun Pan --- v4: add missing changes, and split to 5/11, 6/11, 7/11 v3: use tcg_gen_gvec_mul() v2: fix coding style use Power ISA 3.1 flag tcg/ppc/tcg-target.h | 2 ++ tcg/ppc/tcg

[PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions

This patch series add several newly introduced 32/64-bit vector instructions in Power ISA 3.1. Power ISA 3.1 flag is introduced in this version. In v4 version, coding style issues are fixed, community reviews/suggestions are taken into consideration. Lijun Pan (11): target/ppc: Introduce Power

[PATCH v4 08/11] target/ppc: add vmulh{su}w instructions

vmulhsw: Vector Multiply High Signed Word vmulhuw: Vector Multiply High Unsigned Word Signed-off-by: Lijun Pan --- Reviewed-by: Richard Henderson v3: inline the helper_vmulh{su}w multiply directly instead of using macro v2: fix coding style use Power ISA 3.1 flag target/ppc/helper.h

[PATCH v4 02/11] target/ppc: Enable Power ISA 3.1

This patch enables the Power ISA 3.1 in QEMU. Signed-off-by: Lijun Pan --- v4: split to 01/11 and 02/11 v2: add Power ISA 3.1 flag target/ppc/cpu.h| 2 +- target/ppc/translate_init.inc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b

[PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition

Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions. Signed-off-by: Lijun Pan --- v4: add missing changes, and split to 5/11, 6/11, 7/11 v3: use tcg_gen_gvec_mul() v2: fix coding style use Power ISA 3.1 flag include/elf.h | 1 + 1 file changed, 1 insertion(+) diff --git a

[PATCH v4 01/11] target/ppc: Introduce Power ISA 3.1 flag

This flag will be used for Power10 instructions. Signed-off-by: Lijun Pan --- v4: split to 01/11 and 02/11 v2: add Power ISA 3.1 flag target/ppc/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 1988b436cb..a5e9c08dcc 100644 --- a/target/ppc

Re: [PATCH v3 8/8] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions

> On Jun 25, 2020, at 1:37 PM, Richard Henderson > wrote: > > On 6/25/20 10:00 AM, Lijun Pan wrote: >> +#define VDIV_MOD_DO(name, op, element, sign, bit) \ >> +void helper_v##name(ppc_avr_t *r, pp

Re: [PATCH v3 4/8] target/ppc: add vmulld instruction

> On Jun 25, 2020, at 1:25 PM, Richard Henderson > wrote: > > On 6/25/20 10:00 AM, Lijun Pan wrote: >> vmulld: Vector Multiply Low Doubleword. >> >> Signed-off-by: Lijun Pan >> --- >> v3: use tcg_gen_gvec_mul() >> >> target/ppc/tran

Re: [PATCH v3 1/8] target/ppc: Introduce Power ISA 3.1 flag

> On Jun 25, 2020, at 12:40 PM, Richard Henderson > wrote: > > On 6/25/20 10:00 AM, Lijun Pan wrote: >> +/* POWER ISA 3.1 >> */ >> +PPC2_ISA310= 0x0010ULL, > &g

Re: [PATCH v3 2/8] target/ppc: add byte-reverse br[dwh] instructions

> On Jun 25, 2020, at 12:42 PM, Richard Henderson > wrote: > > On 6/25/20 10:00 AM, Lijun Pan wrote: >> +static void gen_brh(DisasContext *ctx) >> +{ >> +TCGv_i64 t0 = tcg_temp_new_i64(); >> +TCGv_i64 t1 = tcg_temp_new_i64(); &g

[PATCH v3 5/8] target/ppc: add vmulh{su}w instructions

vmulhsw: Vector Multiply High Signed Word vmulhuw: Vector Multiply High Unsigned Word Signed-off-by: Lijun Pan --- v3: inline the helper_vmulh{su}w multiply directly instead of using macro target/ppc/helper.h | 2 ++ target/ppc/int_helper.c | 19

[PATCH v3 7/8] target/ppc: add vmulh{su}d instructions

vmulhsd: Vector Multiply High Signed Doubleword vmulhud: Vector Multiply High Unsigned Doubleword Signed-off-by: Lijun Pan --- v3: simplify helper_vmulh{su}d target/ppc/helper.h | 2 ++ target/ppc/int_helper.c | 16 target/ppc/translate/vmx

[PATCH v3 2/8] target/ppc: add byte-reverse br[dwh] instructions

POWER ISA 3.1 introduces following byte-reverse instructions: brd: Byte-Reverse Doubleword X-form brw: Byte-Reverse Word X-form brh: Byte-Reverse Halfword X-form Signed-off-by: Lijun Pan --- v3: fix the store issue in br[dwh] simplify brw implementation add "if defined(TARGET_

[PATCH v3 3/8] target/ppc: convert vmuluwm to tcg_gen_gvec_mul

Convert the original implementation of vmuluwm to the more generic tcg_gen_gvec_mul. Signed-off-by: Lijun Pan --- v3: newly introduced. target/ppc/helper.h | 1 - target/ppc/int_helper.c | 13 - target/ppc/translate/vmx-impl.inc.c | 2 +- 3 files

[PATCH v3 6/8] fix the prototype of muls64/mulu64

The prototypes of muls64/mulu64 in host-utils.h should match the definitions in host-utils.c Signed-off-by: Lijun Pan --- include/qemu/host-utils.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index 4cd170e6cd

[PATCH v3 8/8] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions

Doubleword Signed-off-by: Lijun Pan --- v3: add missing divided-by-zero, divided-by-(-1) handling target/ppc/helper.h | 8 target/ppc/int_helper.c | 26 ++ target/ppc/translate.c | 3 +++ target/ppc/translate/vmx-impl.inc.c

[PATCH v3 0/8] Add several Power ISA 3.1 32/64-bit vector instructions

This patch series add several newly introduced 32/64-bit vector instructions in Power ISA 3.1. Power ISA 3.1 flag is introduced in this version. In v3 version, coding style issues are fixed, community reviews/suggestions are taken into consideration. Lijun Pan (8): target/ppc: Introduce Power

[PATCH v3 1/8] target/ppc: Introduce Power ISA 3.1 flag

This flag will be used for Power10 instructions. Signed-off-by: Lijun Pan --- target/ppc/cpu.h| 4 +++- target/ppc/translate_init.inc.c | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 1988b436cb..ebb5a0811a 100644

[PATCH v3 4/8] target/ppc: add vmulld instruction

vmulld: Vector Multiply Low Doubleword. Signed-off-by: Lijun Pan --- v3: use tcg_gen_gvec_mul() target/ppc/translate/vmx-impl.inc.c | 1 + target/ppc/translate/vmx-ops.inc.c | 4 tcg/ppc/tcg-target.h| 2 ++ tcg/ppc/tcg-target.inc.c| 7 +-- 4 files changed

[PATCH v3] target/ppc: add vmsumudm vmsumcud instructions

vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo VA-form. vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned Doubleword VA-form. Signed-off-by: Lijun Pan --- v3: implement vmsumudm/vmsumcud through int128 functions, suggested by Ric

Re: [PATCH 3/6] targetc/ppc: add vmulh{su}w instructions

> On Jun 18, 2020, at 6:29 PM, Richard Henderson > wrote: > > On 6/12/20 9:20 PM, Lijun Pan wrote: >> +#define VMULH_DO(name, op, element, cast_orig, cast_temp) \ >> +void helper_vmulh##name(ppc_avr_t *r, pp

Re: [PATCH 2/6] target/ppc: add vmulld instruction

> On Jun 18, 2020, at 6:27 PM, Richard Henderson > wrote: > > On 6/12/20 9:20 PM, Lijun Pan wrote: >> vmulld: Vector Multiply Low Doubleword. >> >> Signed-off-by: Lijun Pan >> --- >> target/ppc/helper.h | 1 + >> target/

Re: [PATCH 1/6] target/ppc: add byte-reverse br[dwh] instructions

> On Jun 18, 2020, at 6:19 PM, Richard Henderson > wrote: > > On 6/12/20 9:20 PM, Lijun Pan wrote: >> POWER ISA 3.1 introduces following byte-reverse instructions: >> brd: Byte-Reverse Doubleword X-form >> brw: Byte-Reverse Word X-form >> brh: Byte-Rever

Re: [PATCH v2] target/ppc: add vmsumudm vmsumcud instructions

> On Jun 18, 2020, at 6:09 PM, Richard Henderson > wrote: > > On 6/15/20 1:53 PM, Lijun Pan wrote: >>>> +static inline void uint128_add(uint64_t ah, uint64_t al, uint64_t bh, >>>> + uint64_t bl, uint64_t *rh, uint64_t *rl, uint64_t *ca) >>

Re: [PATCH v2 0/7] Add several Power ISA 3.1 32/64-bit vector instructions

> On Jun 17, 2020, at 7:42 PM, no-re...@patchew.org wrote: > > Patchew URL: > https://patchew.org/QEMU/20200618001127.34438-1-...@linux.ibm.com/ > > > > Hi, > > This series failed the asan build test. Please find the testing commands and > their output below. If you have Docker installed,

[PATCH v2 6/7] target/ppc: add vmulh{su}d instructions

vmulhsd: Vector Multiply High Signed Doubleword vmulhud: Vector Multiply High Unsigned Doubleword Signed-off-by: Lijun Pan --- v2: fix coding style use Power ISA 3.1 flag target/ppc/helper.h | 2 ++ target/ppc/int_helper.c | 24 target

[PATCH v2 4/7] target/ppc: add vmulh{su}w instructions

vmulhsw: Vector Multiply High Signed Word vmulhuw: Vector Multiply High Unsigned Word Signed-off-by: Lijun Pan --- v2: fix coding style use Power ISA 3.1 flag target/ppc/helper.h | 2 ++ target/ppc/int_helper.c | 14 ++ target/ppc/translate/vmx

[PATCH v2 1/7] target/ppc: Introduce Power ISA 3.1 flag

This flag will be used for Power10 instructions. Signed-off-by: Lijun Pan --- v2: add Power ISA 3.1 flag target/ppc/cpu.h| 4 +++- target/ppc/translate_init.inc.c | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index

[PATCH v2 7/7] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions

Doubleword Signed-off-by: Lijun Pan --- v2: fix coding style use Power ISA 3.1 flag target/ppc/helper.h | 8 target/ppc/int_helper.c | 19 +++ target/ppc/translate.c | 3 +++ target/ppc/translate/vmx-impl.inc.c | 15

[PATCH v2 5/7] fix the prototype of muls64/mulu64

The prototypes of muls64/mulu64 in host-utils.h should match the definitions in host-utils.c Signed-off-by: Lijun Pan --- v2: no change include/qemu/host-utils.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index

[PATCH v2 2/7] target/ppc: add byte-reverse br[dwh] instructions

POWER ISA 3.1 introduces following byte-reverse instructions: brd: Byte-Reverse Doubleword X-form brw: Byte-Reverse Word X-form brh: Byte-Reverse Halfword X-form Signed-off-by: Lijun Pan --- v2: fix coding style use Power ISA 3.1 flag target/ppc/translate.c | 62

[PATCH v2 3/7] target/ppc: add vmulld instruction

vmulld: Vector Multiply Low Doubleword. Signed-off-by: Lijun Pan --- v2: fix coding style use Power ISA 3.1 flag target/ppc/helper.h | 1 + target/ppc/int_helper.c | 1 + target/ppc/translate/vmx-impl.inc.c | 1 + target/ppc/translate/vmx-ops.inc.c | 4 4

[PATCH v2 0/7] Add several Power ISA 3.1 32/64-bit vector instructions

This patch series add several newly introduced 32/64-bit vector instructions in Power ISA 3.1. Power ISA 3.1 flag is introduced in this version. Coding style issues are fixed in this version. Lijun Pan (7): target/ppc: Introduce Power ISA 3.1 flag target/ppc: add byte-reverse br[dwh

Re: [PATCH v2] target/ppc: add vmsumudm vmsumcud instructions

> On Jun 15, 2020, at 11:12 AM, Richard Henderson > wrote: > > On 6/12/20 8:55 PM, Lijun Pan wrote: >> vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo >> VA-form. >> vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-

Re: [PATCH 0/6] Add several Power ISA 3.1 32/64-bit vector instructions

> On Jun 15, 2020, at 12:36 PM, Cédric Le Goater wrote: > > Hello, > > On 6/13/20 6:20 AM, Lijun Pan wrote: >> This patch series add several newly introduced 32/64-bit vector >> instructions in Power ISA 3.1. The newly added instructions are >> flagged as IS

[PATCH 4/6] target/ppc: add vmulh{su}d instructions

vmulhsd: Vector Multiply High Signed Doubleword vmulhud: Vector Multiply High Unsigned Doubleword Signed-off-by: Lijun Pan --- target/ppc/helper.h | 2 ++ target/ppc/int_helper.c | 24 target/ppc/translate/vmx-impl.inc.c | 2 ++ target/ppc

[PATCH 0/6] Add several Power ISA 3.1 32/64-bit vector instructions

been fully enabled in QEMU yet. When Power ISA 3.1 and next generation processor are fully supported, the flags should be changed. Lijun Pan (6): target/ppc: add byte-reverse br[dwh] instructions target/ppc: add vmulld instruction targetc/ppc: add vmulh{su}w instructions target/ppc: add

[PATCH 3/6] targetc/ppc: add vmulh{su}w instructions

vmulhsw: Vector Multiply High Signed Word vmulhuw: Vector Multiply High Unsigned Word Signed-off-by: Lijun Pan --- target/ppc/helper.h | 2 ++ target/ppc/int_helper.c | 14 ++ target/ppc/translate/vmx-impl.inc.c | 6 ++ target/ppc/translate/vmx

[PATCH 6/6] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions

Doubleword Signed-off-by: Lijun Pan --- target/ppc/helper.h | 8 target/ppc/int_helper.c | 19 +++ target/ppc/translate.c | 3 +++ target/ppc/translate/vmx-impl.inc.c | 15 +++ target/ppc/translate/vmx-ops.inc.c | 15

[PATCH 5/6] fix the prototype of muls64/mulu64

The prototypes of muls64/mulu64 in host-utils.h should match the definitions in host-utils.c Signed-off-by: Lijun Pan --- include/qemu/host-utils.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index 4cd170e6cd

[PATCH 2/6] target/ppc: add vmulld instruction

vmulld: Vector Multiply Low Doubleword. Signed-off-by: Lijun Pan --- target/ppc/helper.h | 1 + target/ppc/int_helper.c | 1 + target/ppc/translate/vmx-impl.inc.c | 1 + target/ppc/translate/vmx-ops.inc.c | 1 + 4 files changed, 4 insertions(+) diff --git a/target

[PATCH 1/6] target/ppc: add byte-reverse br[dwh] instructions

POWER ISA 3.1 introduces following byte-reverse instructions: brd: Byte-Reverse Doubleword X-form brw: Byte-Reverse Word X-form brh: Byte-Reverse Halfword X-form Signed-off-by: Lijun Pan --- target/ppc/translate.c | 62 ++ 1 file changed, 62 insertions

[PATCH v2] target/ppc: add vmsumudm vmsumcud instructions

vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo VA-form. vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned Doubleword VA-form. Signed-off-by: Lijun Pan --- v2: move vmsumcudm() to qemu/int128.h as Richard Henderson suggested, also re

[PATCH 1/1] target/ppc: add vmsumudm vmsumcud instructions

vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo VA-form. vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned Doubleword VA-form. Signed-off-by: Lijun Pan --- disas/ppc.c | 2 ++ include/qemu/host-utils.h