On 5/30/25 07:23, Thomas Huth wrote:
Hi Guenter et al.,
I was trying to create a functional test for the "highbank" and "midway" arm machines of
QEMU, and only succeeded after lots of trial and error to boot something on the "highbank" machine.
Peter mentioned on IRC that he also does not t
On 4/11/25 00:40, Nicholas Piggin wrote:
On Sun Apr 6, 2025 at 12:00 AM AEST, Guenter Roeck wrote:
According to the XHCI specification, ERSTBA should be written in Low-High
order. The Linux kernel writes the high word first. This results in an
initialization failure.
This should probably be
On 4/11/25 00:40, Nicholas Piggin wrote:
On Sun Apr 6, 2025 at 12:00 AM AEST, Guenter Roeck wrote:
According to the XHCI specification, ERSTBA should be written in Low-High
order. The Linux kernel writes the high word first. This results in an
initialization failure.
This should probably be
On 4/8/25 14:56, Bernhard Beschow wrote:
Tt turns out that sabrelite has the same problem.
Did it work with QEMU 9.2?
No, the pcie interfaces on sabrelite don't instantiate for me with qemu 9.2
(9.2.3,
more specifically). I see the pcie root port, but nothing behind it.
You need to add `
On 4/8/25 12:57, Bernhard Beschow wrote:
Am 8. April 2025 16:09:58 UTC schrieb Guenter Roeck :
On 4/6/25 11:08, Bernhard Beschow wrote:
[ .. ]
Yeah, it works with Buildroot as described in the handbook. When I append
`-netdev user,id=net0 -device virtio-net-pci,netdev=net0` on the cli I
On 4/8/25 12:57, Bernhard Beschow wrote:
Am 8. April 2025 16:09:58 UTC schrieb Guenter Roeck :
On 4/6/25 11:08, Bernhard Beschow wrote:
[ .. ]
Yeah, it works with Buildroot as described in the handbook. When I append
`-netdev user,id=net0 -device virtio-net-pci,netdev=net0` on the cli I
On 4/6/25 11:08, Bernhard Beschow wrote:
[ .. ]
Yeah, it works with Buildroot as described in the handbook. When I append
`-netdev user,id=net0 -device virtio-net-pci,netdev=net0` on the cli I can
`wget http://www.google.com` successfully. When I omit it there is no network
connectivity. This
On 4/6/25 04:03, Bernhard Beschow wrote:
Am 6. April 2025 01:31:49 UTC schrieb Guenter Roeck :
On 4/5/25 12:28, Bernhard Beschow wrote:
Am 5. April 2025 17:26:14 UTC schrieb Guenter Roeck :
On 4/5/25 07:25, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 5/4/25 16:00, Guenter Roeck wrote
On 4/5/25 12:28, Bernhard Beschow wrote:
Am 5. April 2025 17:26:14 UTC schrieb Guenter Roeck :
On 4/5/25 07:25, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 5/4/25 16:00, Guenter Roeck wrote:
This series is needed to support the USB interface on imx8mp-evk when
booting the Linux kernel
Hi Bernhard,
On 4/5/25 12:28, Bernhard Beschow wrote:
Am 5. April 2025 17:26:14 UTC schrieb Guenter Roeck :
On 4/5/25 07:25, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 5/4/25 16:00, Guenter Roeck wrote:
This series is needed to support the USB interface on imx8mp-evk when
booting the
On 4/5/25 07:25, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 5/4/25 16:00, Guenter Roeck wrote:
This series is needed to support the USB interface on imx8mp-evk when
booting the Linux kernel.
According to the XHCI specification, ERSTBA should be written in Low-High
order. The Linux kernel
On 4/5/25 07:25, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 5/4/25 16:00, Guenter Roeck wrote:
This series is needed to support the USB interface on imx8mp-evk when
booting the Linux kernel.
According to the XHCI specification, ERSTBA should be written in Low-High
order. The Linux kernel
t
for dwc3.
--------
Guenter Roeck (2):
hw: usb: xhci: Add property to support writing ERSTBA in high-low order
hw/usb/hcd-dwc3: Set erstba-hi-lo property
hw/usb/hcd-dwc3.c | 1 +
hw/usb/hcd-xhci.c | 8 +++-
hw/usb/hcd-xhci.h | 1 +
3 files changed, 9 insertions(+), 1 deletion(-)
the "Event Ring Segment Table Entry" based on the indication of
ERSTBA_LO written.
Add property to support writing the high word first.
Signed-off-by: Guenter Roeck
---
hw/usb/hcd-xhci.c | 8 +++-
hw/usb/hcd-xhci.h | 1 +
2 files changed, 8 insertions(+), 1 deletion(-)
diff --gi
XHCI core to expect ERSTBA to be written in high-low order.
Signed-off-by: Guenter Roeck
---
hw/usb/hcd-dwc3.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/usb/hcd-dwc3.c b/hw/usb/hcd-dwc3.c
index 0bceee2712..6783d55526 100644
--- a/hw/usb/hcd-dwc3.c
+++ b/hw/usb/hcd-dwc3.c
@@ -603,6 +60
On 3/18/25 09:59, Peter Maydell wrote:
On Sat, 15 Mar 2025 at 14:20, Guenter Roeck wrote:
Without psci_conduit, the Linux kernel crashes almost immediately.
psci: probing for conduit method from DT.
Internal error: Oops - Undefined instruction: 0200 [#1]
PREEMPT SMP
ned-off-by: Guenter Roeck
---
hw/arm/npcm8xx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c
index f182accc47..e5a1929ed7 100644
--- a/hw/arm/npcm8xx.c
+++ b/hw/arm/npcm8xx.c
@@ -346,6 +346,7 @@ static struct arm_boot_info npcm8xx_binfo = {
.s
On 3/10/25 08:27, Philippe Mathieu-Daudé wrote:
On 10/3/25 15:09, BALATON Zoltan wrote:
On Mon, 10 Mar 2025, Philippe Mathieu-Daudé wrote:
The previous commit removed the single use of instance
setting the "endianness" property.
Since classes can register their io_ops with correct
endianness,
On 3/10/25 10:31, Philippe Mathieu-Daudé wrote:
...
Oops... I'm surprised tests passed. Do we have coverage for sdhci on
e500 machines? Or are we only testing them via virtio PCI block storage?
Not sure if that is what you are asking, but I have been testing it with
sdhci-pci for a long time (n
On 11/18/24 08:37, Michael Tokarev wrote:
12.11.2024 20:01, Guenter Roeck wrote:
The ClearPortFeature control message fails for PORT_POWER because there
is no break; at the end of the case statement, causing it to fall through
to the failure handler. Add the missing break; to solve the problem
additional USB bus.
Reviewed-by: Cédric Le Goater
Signed-off-by: Guenter Roeck
---
Changes since RFC:
- Rebased to v9.1.0-1673-g134b443512
- Added Reviewed-by: tag
- Added explanation for not using EHCI companion mode
hw/arm/aspeed_ast2400.c | 14 ++
1 file changed, 14 insertions
and use EHCI
companion mode on the second EHCI interface. Support this by moving the
property initialization to the Aspeed class initialization code. Since the
USB ports are part of the SoC and always present, set user_creatable to
false for the Aspeed UHCI controller.
Signed-off-by: Guenter Roeck
hcd-uhci-sysbus will require more memory than hcd-uhci-pci
since registers for some hardware (specifically Aspeed) don't
map 1:1.
Signed-off-by: Guenter Roeck
---
Changes since RFC:
- Rebased to v9.1.0-1673-g134b443512
hw/usb/hcd-uhci.c | 2 +-
1 file changed, 1 insertion(+), 1 del
Signed-off-by: Guenter Roeck
---
Changes since RFC:
- Rebased to v9.1.0-1673-g134b443512
hw/arm/Kconfig | 1 +
hw/usb/Kconfig | 4 ++
hw/usb/hcd-uhci-sysbus.c | 100 +++
hw/usb/hcd-uhci-sysbus.h | 23 +
hw/usb/meson.build
Fix reported checkpatch issues to prepare for next patches
in the series.
No functional change.
Reviewed-by: Cédric Le Goater
Signed-off-by: Guenter Roeck
---
Changes since RFC:
- Rebased to v9.1.0-1673-g134b443512
- Added Reviewed-by: tag
hw/usb/hcd-uhci.c | 90
Add UHCI support for the ast2600 SoC. With this patch, UHCI support
is successfully enabled on the rainier-bmc and ast2600-evb machines.
Signed-off-by: Guenter Roeck
---
Changes since RFC:
- Rebased to v9.1.0-1673-g134b443512
- Use EHCI companion mode
hw/arm/aspeed_ast2600.c | 20
, bcdDevice= 0.00
To distinguish v1 from v2 instantiated hubs, the device version is set to
2.01 (from 1.01) if the hub ist instantiated as USB v2 hub. The product
name is set to "QEMU USB v2.0 Hub".
Signed-off-by: Guenter Roeck
---
Changes since RFC:
- New patch
hw/usb/dev-
The ClearPortFeature control message fails for PORT_POWER because there
is no break; at the end of the case statement, causing it to fall through
to the failure handler. Add the missing break; to solve the problem.
Signed-off-by: Guenter Roeck
---
Change from RFC:
New patch
hw/usb/dev
ization of vt82c686-uhci-pci.c
which if instantiated caused a machine crash
- Instantiate UHCI controllers as companion devices on AST2600 machines
--------
Guenter Roeck (10):
usb/uhci: checkpatch cleanup
usb/uhci: Introdu
Some machines (like Aspeed ARM) only have a sysbus UHCI controller.
The current UHCI implementation only supports PCI based UHCI controllers.
Move the UHCI-PCI device code into a separate file so that it is possible
to create a sysbus UHCI device without PCI dependency.
Signed-off-by: Guenter
Introduce defines for UHCI registers to simplify adding register access
in subsequent patches of the series.
No functional change.
Reviewed-by: Cédric Le Goater
Signed-off-by: Guenter Roeck
---
Changes since RFC:
- Rebased to v9.1.0-1673-g134b443512
- Added Reviewed-by: tag
hw/usb/hcd-uhci.c
Oops, sorry, the subject should have started with "[PATCH 00/10]"
Why do I always see that one second after sending :-(
Guenter
On 11/12/24 08:56, Guenter Roeck wrote:
Some machines (like Aspeed ARM) only support a sysbus UHCI controller.
The current UHCI implementation in qemu onl
Fix reported checkpatch issues to prepare for next patches
in the series.
No functional change.
Reviewed-by: Cédric Le Goater
Signed-off-by: Guenter Roeck
---
Changes since RFC:
- Rebased to v9.1.0-1673-g134b443512
- Added Reviewed-by: tag
hw/usb/hcd-uhci.c | 90
which if instantiated caused a machine crash
- Instantiate UHCI controllers as companion devices on AST2600 machines
--------
Guenter Roeck (10):
usb/uhci: checkpatch cleanup
usb/uhci: Introduce and use register defines
usb/uhci
Introduce defines for UHCI registers to simplify adding register access
in subsequent patches of the series.
No functional change.
Reviewed-by: Cédric Le Goater
Signed-off-by: Guenter Roeck
---
Changes since RFC:
- Rebased to v9.1.0-1673-g134b443512
- Added Reviewed-by: tag
hw/usb/hcd-uhci.c
Signed-off-by: Guenter Roeck
---
Changes since RFC:
- Rebased to v9.1.0-1673-g134b443512
hw/arm/Kconfig | 1 +
hw/usb/Kconfig | 4 ++
hw/usb/hcd-uhci-sysbus.c | 100 +++
hw/usb/hcd-uhci-sysbus.h | 23 +
hw/usb/meson.build
and use EHCI
companion mode on the second EHCI interface. Support this by moving the
property initialization to the Aspeed class initialization code. Since the
USB ports are part of the SoC and always present, set user_creatable to
false for the Aspeed UHCI controller.
Signed-off-by: Guenter Roeck
additional USB bus.
Reviewed-by: Cédric Le Goater
Signed-off-by: Guenter Roeck
---
Changes since RFC:
- Rebased to v9.1.0-1673-g134b443512
- Added Reviewed-by: tag
- Added explanation for not using EHCI companion mode
hw/arm/aspeed_ast2400.c | 14 ++
1 file changed, 14 insertions
Some machines (like Aspeed ARM) only have a sysbus UHCI controller.
The current UHCI implementation only supports PCI based UHCI controllers.
Move the UHCI-PCI device code into a separate file so that it is possible
to create a sysbus UHCI device without PCI dependency.
Signed-off-by: Guenter
hcd-uhci-sysbus will require more memory than hcd-uhci-pci
since registers for some hardware (specifically Aspeed) don't
map 1:1.
Signed-off-by: Guenter Roeck
---
Changes since RFC:
- Rebased to v9.1.0-1673-g134b443512
hw/usb/hcd-uhci.c | 2 +-
1 file changed, 1 insertion(+), 1 del
, bcdDevice= 0.00
To distinguish v1 from v2 instantiated hubs, the device version is set to
2.01 (from 1.01) if the hub ist instantiated as USB v2 hub. The product
name is set to "QEMU USB v2.0 Hub".
Signed-off-by: Guenter Roeck
---
Changes since RFC:
- New patch
hw/usb/dev-
Add UHCI support for the ast2600 SoC. With this patch, UHCI support
is successfully enabled on the rainier-bmc and ast2600-evb machines.
Signed-off-by: Guenter Roeck
---
Changes since RFC:
- Rebased to v9.1.0-1673-g134b443512
- Use EHCI companion mode
hw/arm/aspeed_ast2600.c | 20
Hi Thomas,
On 11/11/24 22:32, Thomas Huth wrote:
On 06/09/2024 14.25, Guenter Roeck wrote:
Some machines (like Aspeed ARM) only have a sysbus UHCI controller.
The current UHCI implementation only supports PCI based UHCI controllers.
Move the UHCI-PCI device code into a separate file so that it
t;
> Signed-off-by: Bernhard Beschow
Tested-by: Guenter Roeck
On Sat, Nov 02, 2024 at 01:57:23PM +0100, Bernhard Beschow wrote:
> Prefer named constants over magic values for better readability.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Bernhard Beschow
Tested-by: Guenter Roeck
ydell
> Signed-off-by: Bernhard Beschow
Tested-by: Guenter Roeck
ice model which breaks
> migration compatibility for the following machines:
> * smdkc210
> * realview-*
> * vexpress-*
> * kzm
> * mps2-*
>
> While breaking migration ABI, fix the size of the MII registers to be 16 bit,
> as defined by IEEE 802.3u.
>
> Signed-off-by: Bernhard Beschow
Tested-by: Guenter Roeck
>
> Some migration state how resides in the new device model which breaks
> migration
> compatibility for the following machines:
> * imx25-pdk
> * sabrelite
> * mcimx7d-sabre
> * mcimx6ul-evk
>
> Signed-off-by: Bernhard Beschow
Tested-by: Guenter Roeck
boot areas.
Cc: Jan Luebbe
Fixes: e554e45b4478 ("aspeed: Tune eMMC device properties to reflect
HW strapping")
Signed-off-by: Cédric Le Goater
Tested-by: Guenter Roeck
---
hw/arm/aspeed.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/arm/as
On 10/28/24 01:41, Jan Lübbe wrote:
On Sun, 2024-10-27 at 20:32 -0700, Guenter Roeck wrote:
On 10/27/24 15:26, Cédric Le Goater wrote:
On 10/27/24 23:11, Guenter Roeck wrote:
On 10/27/24 14:13, Cédric Le Goater wrote:
On 10/26/24 17:32, Guenter Roeck wrote:
On 10/26/24 03:02, Cédric Le
On 10/27/24 15:26, Cédric Le Goater wrote:
On 10/27/24 23:11, Guenter Roeck wrote:
On 10/27/24 14:13, Cédric Le Goater wrote:
On 10/26/24 17:32, Guenter Roeck wrote:
On 10/26/24 03:02, Cédric Le Goater wrote:
[ ... ]
I don't mind a single file. What bothers me is that the partitioni
On 10/27/24 14:13, Cédric Le Goater wrote:
On 10/26/24 17:32, Guenter Roeck wrote:
On 10/26/24 03:02, Cédric Le Goater wrote:
[ ... ]
I don't mind a single file. What bothers me is that the partitioning is made
mandatory for ast2600 even if not used.
Our only use case, in 2019, was to
boot_emmc ? 0x1 << 3 : 0x0);
(I am not saying this is correct)
Works for me, though, and it is much better than mandating the existence
of boot partitions.
If you end up submitting those patches, please feel free to add
Tested-by: Guenter Roeck
Thanks,
Guenter
On 10/25/24 21:47, Philippe Mathieu-Daudé wrote:
On 25/10/24 12:25, Jan Lübbe wrote:
On Fri, 2024-10-25 at 06:59 -0700, Guenter Roeck wrote:
On 10/25/24 02:57, Jan Lübbe wrote:
On Fri, 2024-10-25 at 08:55 +0200, Cédric Le Goater wrote:
On 10/24/24 19:59, Philippe Mathieu-Daudé wrote:
Cc
On 10/25/24 08:25, Jan Lübbe wrote:
On Fri, 2024-10-25 at 06:59 -0700, Guenter Roeck wrote:
On 10/25/24 02:57, Jan Lübbe wrote:
On Fri, 2024-10-25 at 08:55 +0200, Cédric Le Goater wrote:
On 10/24/24 19:59, Philippe Mathieu-Daudé wrote:
Cc'ing Jan.
On 22/10/24 12:04, Guenter Roeck wrote
On 10/25/24 02:57, Jan Lübbe wrote:
Hi,
On Fri, 2024-10-25 at 08:55 +0200, Cédric Le Goater wrote:
On 10/24/24 19:59, Philippe Mathieu-Daudé wrote:
Cc'ing Jan.
On 22/10/24 12:04, Guenter Roeck wrote:
On 10/21/24 21:09, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 21/10/24 11:02, Gu
On 10/24/24 10:53, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 24/10/24 01:04, Guenter Roeck wrote:
On 10/23/24 20:27, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 23/10/24 19:24, Guenter Roeck wrote:
Hi,
On Fri, Jun 28, 2024 at 09:01:27AM +0200, Philippe Mathieu-Daudé wrote:
Signed-off
On 10/24/24 12:13, Guenter Roeck wrote:
On 10/24/24 10:53, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 24/10/24 01:04, Guenter Roeck wrote:
On 10/23/24 20:27, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 23/10/24 19:24, Guenter Roeck wrote:
Hi,
On Fri, Jun 28, 2024 at 09:01:27AM +0200
On 10/23/24 20:27, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 23/10/24 19:24, Guenter Roeck wrote:
Hi,
On Fri, Jun 28, 2024 at 09:01:27AM +0200, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
---
This patch results in:
[ 5.976133
Hi,
On Fri, Jun 28, 2024 at 09:01:27AM +0200, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Cédric Le Goater
> ---
This patch results in:
[5.976133] Waiting for root device /dev/mmcblk0...
[6.501462] mmc0: error -38 whilst initialising SD card
[
On 10/21/24 21:09, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 21/10/24 11:02, Guenter Roeck wrote:
Unrelated to this, but I found that the sd emulation in 9.1 is also broken
for loongarch and sifive_u, and partially for ast2600-evb (it has two
controllers, with one of them no longer working
On 10/21/24 21:09, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 21/10/24 11:02, Guenter Roeck wrote:
Unrelated to this, but I found that the sd emulation in 9.1 is also broken
for loongarch and sifive_u, and partially for ast2600-evb (it has two
controllers, with one of them no longer working
On 10/21/24 07:36, Guenter Roeck wrote:
On 10/21/24 03:43, BALATON Zoltan wrote:
(Resend with fixed ppc list address.)
On Sun, 20 Oct 2024, Guenter Roeck wrote:
Hi,
On Fri, Jul 19, 2024 at 11:07:01AM +1000, Richard Henderson wrote:
We can determine at translation time whether the insn is or
On 10/21/24 03:43, BALATON Zoltan wrote:
(Resend with fixed ppc list address.)
On Sun, 20 Oct 2024, Guenter Roeck wrote:
Hi,
On Fri, Jul 19, 2024 at 11:07:01AM +1000, Richard Henderson wrote:
We can determine at translation time whether the insn is or
is not dbczl. We must retain a runtime
the
culling of the OMAP/PXA2xx/strongarm machines.
For these tests I'm indebted to Guenter Roeck, who has kindly
built and made available the kernel images, rootfs, etc and
documented the commands needed to boot them. All I've done
here is wrap those up into test cases in our testcase
fr
On 10/20/24 23:57, Paolo Bonzini wrote:
On 10/21/24 03:49, Guenter Roeck wrote:
Hi,
On Sat, Jun 08, 2024 at 10:40:58AM +0200, Paolo Bonzini wrote:
This is already partly implemented due to VLDMXCSR and VSTMXCSR; finish
the job.
Signed-off-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Hi,
On Sat, Jun 08, 2024 at 10:40:58AM +0200, Paolo Bonzini wrote:
> This is already partly implemented due to VLDMXCSR and VSTMXCSR; finish
> the job.
>
> Signed-off-by: Paolo Bonzini
> Reviewed-by: Richard Henderson
While testing qemu v9.1, I noticed the following crash when testing
qemu-sy
Hi,
On Fri, Jul 19, 2024 at 11:07:01AM +1000, Richard Henderson wrote:
> We can determine at translation time whether the insn is or
> is not dbczl. We must retain a runtime check against the
> HID5 register, but we can move that to a separate function
> that never affects other ppc models.
>
>
ype_t's definition out of sd.h and into sd.c, which is the
only place that uses it.
Cc: qemu-sta...@nongnu.org
Fixes: 1ab08790bb75 ("hw/sd/sdcard: Store command type in SDProto")
Signed-off-by: Peter Maydell
Tested-by: Guenter Roeck
On 10/17/24 07:29, Peter Maydell wrote:
On Thu, 17 Oct 2024 at 15:12, Guenter Roeck wrote:
On 10/17/24 05:42, Peter Maydell wrote:
On Tue, 15 Oct 2024 at 19:12, Guenter Roeck wrote:
Please let me know if https://github.com/groeck/linux-test-downloads.git
meets your needs. For now I added
On 10/17/24 05:42, Peter Maydell wrote:
On Tue, 15 Oct 2024 at 19:12, Guenter Roeck wrote:
Please let me know if https://github.com/groeck/linux-test-downloads.git
meets your needs. For now I added 'collie'. I'll add more after it is
in a state that is useful for you.
Ye
On 10/15/24 10:35, Peter Maydell wrote:
On Tue, 15 Oct 2024 at 18:30, Guenter Roeck wrote:
On 10/15/24 10:13, Peter Maydell wrote:
On Fri, 8 Mar 2024 at 15:41, Peter Maydell wrote:
Thanks to everybody for your input on this thread. My
proposal is to drop from QEMU:
* all the PXA2xx
On 10/15/24 10:13, Peter Maydell wrote:
On Fri, 8 Mar 2024 at 15:41, Peter Maydell wrote:
Thanks to everybody for your input on this thread. My
proposal is to drop from QEMU:
* all the PXA2xx machines
* all the OMAP2 machines
* the cheetah OMAP1 machine
leaving (at least for now) sx1, sx
On 10/12/24 07:06, Bernhard Beschow wrote:
Am 12. Oktober 2024 09:40:27 UTC schrieb Thomas Huth :
On 12/10/2024 00.48, Philippe Mathieu-Daudé wrote:
On 11/10/24 05:23, Thomas Huth wrote:
On 03/05/2024 23.34, Guenter Roeck wrote:
Hi,
On Thu, Feb 08, 2024 at 07:12:40PM +0100, Philippe
, bcdDevice= 0.00
To distinguish v1 from v2 instantiated hubs, the device version is set to
2.01 (from 1.01) if the hub ist instantiated as USB v2 hub. The product
name is set to "QEMU USB v2.0 Hub".
Signed-off-by: Guenter Roeck
---
hw/usb/dev-
riority.
Thanks,
Guenter
Regards,
Niek
On Mon, Sep 9, 2024 at 11:33 AM Gerd Hoffmann mailto:kra...@redhat.com>> wrote:
On Sun, Sep 08, 2024 at 11:36:18AM GMT, Guenter Roeck wrote:
> Hi,
>
> the Allwinner H3 USB port qemu emulation creates separate USB ports
On 9/11/24 10:33, Cédric Le Goater wrote:
On 9/9/24 17:10, Guenter Roeck wrote:
On 9/9/24 04:20, Joel Stanley wrote:
On Sat, 31 Aug 2024 at 05:41, Guenter Roeck wrote:
On Fri, Aug 30, 2024 at 10:09:25AM +0200, Cédric Le Goater wrote:
Hello,
I solved the problem by adding support for IBM
On Mon, Sep 09, 2024 at 05:45:35PM +0200, Philippe Mathieu-Daudé wrote:
> On 9/9/24 17:02, Peter Maydell wrote:
> > On Mon, 9 Sept 2024 at 15:55, Guenter Roeck wrote:
> > >
> > > On 9/9/24 06:40, Philippe Mathieu-Daudé wrote:
> > > > Hi,
> > >
On 9/9/24 04:20, Joel Stanley wrote:
On Sat, 31 Aug 2024 at 05:41, Guenter Roeck wrote:
On Fri, Aug 30, 2024 at 10:09:25AM +0200, Cédric Le Goater wrote:
Hello,
I solved the problem by adding support for IBM Bonnell (which instantiates
the TPM chip through its devicetree file, similar to
On 9/9/24 06:40, Philippe Mathieu-Daudé wrote:
Hi,
On 3/9/24 18:06, Peter Maydell wrote:
This patchset removes the various Arm machines which we deprecated
for the 9.0 release and are therefore allowed to remove for the 9.2
release:
akita, borzoi, cheetah, connex, mainstone, n800, n810,
spi
Hi,
the Allwinner H3 USB port qemu emulation creates separate USB ports
for its EHCI and OHCI controllers, resulting in a total of 8 USB ports.
>From the orangepi-pc emulation:
# lsusb
Bus 005 Device 001: ID 1d6b:0002
Bus 003 Device 001: ID 1d6b:0002
Bus 001 Device 001: ID 1d6b:0002
Bus 008 Devic
: Philippe Mathieu-Daudé
Reviewed-by: Guenter Roeck
ogical change intended.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Guenter Roeck
On 9/6/24 07:49, Cédric Le Goater wrote:
Joel,
Would have access to a Bonnell BMC ? To get the HW strapping
register values.
On 9/6/24 14:35, Guenter Roeck wrote:
Introduce support for the IBM Bonnell BMC.
Use Rainier machine information for HW strapping and other machine details
since the
Per datasheet, "HIGH AND LOW LIMIT REGISTERS", the lower 4 bit
of the limit registers are unused and always report 0.
The lower 4 bit should not be used for temperature comparisons,
so mask the unused bits before storing the limits.
Signed-off-by: Guenter Roeck
---
hw/sensor/tmp105.c
ned-off-by: Guenter Roeck
---
hw/sensor/tmp105.c | 40 +---
1 file changed, 21 insertions(+), 19 deletions(-)
diff --git a/hw/sensor/tmp105.c b/hw/sensor/tmp105.c
index a8730d0b7f..77fbf2f8d3 100644
--- a/hw/sensor/tmp105.c
+++ b/hw/sensor/tmp105.c
@@ -29
Per datasheet, "ONE-SHOT (OS)", the OS bit always returns 0 when reading
the configuration register.
Signed-off-by: Guenter Roeck
---
hw/sensor/tmp105.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/sensor/tmp105.c b/hw/sensor/tmp105.c
index 77fbf2f8d3..
Fix coding style issues as well as a couple of implementation bugs.
Guenter Roeck (3):
tmp105: Coding style fixes
tmp105: OS (one-shot) bit in configuration register always returns 0
tmp105: Lower 4 bit of limit
Bonnell devicetree file
instantiates a TPM. It is therefore possible to test TPM functionality
without having to instantiate the TPM manually from the Linux command
line.
Signed-off-by: Guenter Roeck
---
hw/arm/aspeed.c | 87 +
1 file changed, 87
Enable UHCI support for ast2400 and ast2500 SoCs. With this patch,
the UHCI port is successfully instantiated on the ast2500-evb machine.
Signed-off-by: Guenter Roeck
---
hw/arm/aspeed_ast2400.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm
Enable UHCO support for the ast2600 SoC. With this patch, the UHCI port
is successfully instantiated on the rainier-bmc and ast2600-evb machines.
Signed-off-by: Guenter Roeck
---
hw/arm/aspeed_ast2600.c | 13 +
include/hw/arm/aspeed_soc.h | 3 +++
2 files changed, 16 insertions
Some machines (like Aspeed ARM) only have a sysbus UHCI controller.
The current UHCI implementation only supports PCI based UHCI controllers.
Move the UHCI-PCI device code into a separate file so that it is possible
to create a sysbus UHCI device without PCI dependency.
Signed-off-by: Guenter
Aspeed uses non-standard UHCI register addresses. On top of that,
registers are 32 bit wide instead of 16 bit.
Map Aspeed UHCI addresses to standard UHCI addresses and where needed
combine/split 32 bit accesses to solve the problem.
Signed-off-by: Guenter Roeck
---
hw/usb/hcd-uhci-sysbus.c
ementation still works. It was also tested on various Aspeed machines
with enabled UHCI ports (ast2500-evb, ast2600-evb, and rainier-bmc).
--------
Guenter Roeck (8):
usb/uhci: checkpatch cleanup
usb/uhci: Introduce and use regist
hcd-uhci-sysbus will require more memory than hcd-uhci-pci
since registers for some hardware (specifically Aspeed) don't
map 1:1.
Signed-off-by: Guenter Roeck
---
hw/usb/hcd-uhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c
Introduce defines for UHCI registers to simplify adding register access
in subsequent patches of the series.
No functional change.
Signed-off-by: Guenter Roeck
---
hw/usb/hcd-uhci.c | 32
include/hw/usb/uhci-regs.h | 11 +++
2 files changed, 27
Signed-off-by: Guenter Roeck
---
hw/arm/Kconfig | 1 +
hw/usb/Kconfig | 4 ++
hw/usb/hcd-uhci-sysbus.c | 100 +++
hw/usb/hcd-uhci-sysbus.h | 23 +
hw/usb/meson.build | 1 +
5 files changed, 129 insertions(+)
create
Fix reported checkpatch issues to prepare for next patches
in the series.
No functional change.
Signed-off-by: Guenter Roeck
---
hw/usb/hcd-uhci.c | 90 +--
1 file changed, 56 insertions(+), 34 deletions(-)
diff --git a/hw/usb/hcd-uhci.c b/hw/usb
On 9/3/24 13:10, Philippe Mathieu-Daudé wrote:
(Cc'ing Guenter who asked to keep the SX1 machine)
On 3/9/24 22:04, Philippe Mathieu-Daudé wrote:
sd_set_cb() was only used by omap2_mmc_init() which
got recently removed. Time to remove it. For historical
background on the me_no_qdev_me_kill_mammo
-us.net/
Reported-by: Guenter Roeck
Signed-off-by: Helge Deller
Fixes: 931adff31478 ("target/hppa: Update cpu_hppa_get/put_psw for hppa64")
Tested-by: Guenter Roeck
Thanks!
Guenter
diff --git a/target/hppa/helper.c b/target/hppa/helper.c
index b79ddd8184..d4b1a3cd5a 100644
--- a/t
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