On 10/20/24 23:57, Paolo Bonzini wrote:
On 10/21/24 03:49, Guenter Roeck wrote:
Hi,
On Sat, Jun 08, 2024 at 10:40:58AM +0200, Paolo Bonzini wrote:
This is already partly implemented due to VLDMXCSR and VSTMXCSR; finish
the job.
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
While testing qemu v9.1, I noticed the following crash when testing
qemu-system-i386
with pentium3 CPU.
Is this enough to fix it?
Yes.
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index ee2a508ae9a..cda32ee6784 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -345,9 +345,9 @@ static void decode_group15(DisasContext *s, CPUX86State
*env, X86OpEntry *entry,
[1] = X86_OP_ENTRYw(RDxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_f3),
[2] = X86_OP_ENTRYr(WRxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_f3
zextT0),
[3] = X86_OP_ENTRYr(WRxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_f3
zextT0),
- [5] = X86_OP_ENTRY0(LFENCE, cpuid(SSE2) p_00),
+ [5] = X86_OP_ENTRY0(LFENCE, cpuid(SSE) p_00),
[6] = X86_OP_ENTRY0(MFENCE, cpuid(SSE2) p_00),
- [7] = X86_OP_ENTRY0(SFENCE, cpuid(SSE2) p_00),
+ [7] = X86_OP_ENTRY0(SFENCE, cpuid(SSE) p_00),
};
static const X86OpEntry group15_mem[8] = {
22: 39 c6 cmp %eax,%esi
24: 0f 82 6a ff ff ff jb 0xffffffffffffff94
2a:* 0f 09 wbinvd <-- trapping instruction
This is a bit weird, as wbinvd is not affected by this patch. However,
a checkout of Linux has
asm volatile("sfence" : :: "memory");
kernel_fpu_end();
}
at the end of lib/raid6/sse1.c and it would indeed be affected by this
patch. SSE2 was not present in Pentium III, but SSE was.
No idea how the 0x0f 0x09 ends up in the log. I wondered about that as well.
Thanks,
Guenter
