On 5/27/25 5:19 PM, Zhao Liu wrote:
On Mon, May 26, 2025 at 06:52:41PM +0800, Ewan Hai wrote:
Date: Mon, 26 May 2025 18:52:41 +0800
From: Ewan Hai
Subject: Re: [RFC 00/10] i386/cpu: Cache CPUID fixup, Intel cache model &
topo CPUID enhencement
On 4/23/25 7:46 PM, Zhao Liu wrote:
On 5/27/25 5:15 PM, Zhao Liu wrote:
On 4/23/25 7:46 PM, Zhao Liu wrote:
Per SDM, 0x8005 leaf is reserved for Intel CPU, and its current
"assert" check blocks adding new cache model for non-AMD CPUs.
Therefore, check the vendor and encode this leaf as all-0 for Intel
CPU. And since Zha
On 4/23/25 7:46 PM, Zhao Liu wrote:
Hi all,
(Since patches 1 and 2 involve changes to x86 vendors other than Intel,
I have also cc'd friends from AMD and Zhaoxin.)
These are the ones I was going to clean up a long time ago:
* Fixup CPUID 0x8005 & 0x8006 for Intel (and Zhaoxin now).
On 4/23/25 7:46 PM, Zhao Liu wrote:
Per SDM, 0x8005 leaf is reserved for Intel CPU, and its current
"assert" check blocks adding new cache model for non-AMD CPUs.
Therefore, check the vendor and encode this leaf as all-0 for Intel
CPU. And since Zhaoxin mostly follows Intel behavior, app
On 5/8/25 5:04 PM, Zhao Liu wrote:
[3] My colleague Alan noticed what appears to be a related problem: if
we launch a guest with '-cpu ,-ht --enable-kvm', which means
explicitly removing the ht flag, but the guest still reports HT(cat
/proc/cpuinfo in linux guest) enabled. In other words, un
Hi Community,
We have observed that the 'ht' feature bit cannot be disabled when QEMU runs
with KVM acceleration.
qemu-system-x86_64 \
--enable-kvm \
-machine q35 \
-cpu host,-ht \
-smp 4 \
-m 4G \
-drive file=rootfs.img,format=raw \
-nographic \
-append 'console=ttyS0 root=/de
On 4/29/25 11:02 AM, Ewan Hai wrote:
Hi Community,
This email contains 3 bugs appear to share the same root cause.
[1] We ran into the following warnings when running QEMU v10.0.0 in TCG mode:
qemu-system-x86_64 \
-machine q35 \
-m 4G -smp 4 \
-kernel ./arch/x86/boot/bzImage
Hi Community,
This email contains 3 bugs appear to share the same root cause.
[1] We ran into the following warnings when running QEMU v10.0.0 in TCG mode:
qemu-system-x86_64 \
-machine q35 \
-m 4G -smp 4 \
-kernel ./arch/x86/boot/bzImage \
-bios /usr/share/ovmf/OVMF.fd \
-drive file=
On 4/24/25 3:25 PM, Michael Tokarev wrote:
On 15.04.2025 05:45, Ewan Hai wrote:
The model number was mistakenly set to 0x0b (11) in commit ff04bc1ac4.
The correct value is 0x5b. This mistake occurred because the extended
model bits in cpuid[eax=0x1].eax were overlooked, and only the base
On 4/23/25 7:46 PM, Zhao Liu wrote:
Per SDM, 0x8005 leaf is reserved for Intel CPU, and its current
"assert" check blocks adding new cache model for non-AMD CPUs.
Therefore, check the vendor and encode this leaf as all-0 for Intel
CPU. And since Zhaoxin mostly follows Intel behavior, app
ppropriate Zhaoxin CPU model(s).
Fixes: ff04bc1ac4 ("target/i386: Introduce Zhaoxin Yongfeng CPU model")
Signed-off-by: Ewan Hai
Reviewed-by: Zhao Liu
---
docs/system/cpu-models-x86.rst.inc | 17 +
target/i386/cpu.c | 12
2 files changed, 29
On 4/14/25 11:05 PM, Zhao Liu wrote:
On Mon, Apr 14, 2025 at 03:53:42AM -0400, Ewan Hai wrote:
Date: Mon, 14 Apr 2025 03:53:42 -0400
From: Ewan Hai
Subject: [PATCH v3] target/i386: Fix model number of Zhaoxin YongFeng vCPU
template
X-Mailer: git-send-email 2.34.1
The model number was
is that vPMU (which relies on the model number) may fail to operate
correctly.
This patch corrects the model field by introducing a new vCPU version.
Fixes: ff04bc1ac4 ("target/i386: Introduce Zhaoxin Yongfeng CPU model")
Signed-off-by: Ewan Hai
---
target/i386/cpu.c | 12 ++
On 4/14/25 2:44 PM, Xiaoyao Li wrote:
On 4/11/2025 3:42 PM, Ewan Hai wrote:
On 4/11/25 11:22 AM, Zhao Liu wrote:
On Thu, Apr 10, 2025 at 10:07:15PM +0800, Ewan Hai wrote:
Date: Thu, 10 Apr 2025 22:07:15 +0800
From: Ewan Hai
Subject: Re: [PATCH v2] target/i386: Fix model number of
On 4/11/25 11:22 AM, Zhao Liu wrote:
On Thu, Apr 10, 2025 at 10:07:15PM +0800, Ewan Hai wrote:
Date: Thu, 10 Apr 2025 22:07:15 +0800
From: Ewan Hai
Subject: Re: [PATCH v2] target/i386: Fix model number of Zhaoxin YongFeng
vCPU template
On 4/10/25 8:22 PM, Paolo Bonzini wrote:
On 4/7
On 4/10/25 8:22 PM, Paolo Bonzini wrote:
On 4/7/25 04:07, Ewan Hai wrote:
The model number was mistakenly set to 0x0b (11) in commit ff04bc1ac4.
The correct value is 0x5b. This mistake occurred because the extended
model bits in cpuid[eax=0x1].eax were overlooked, and only the base
model was
On 4/7/25 4:51 PM, Zhao Liu wrote:
On Tue, Apr 01, 2025 at 11:35:49AM +0800, Ewan Hai wrote:
Date: Tue, 1 Apr 2025 11:35:49 +0800
From: Ewan Hai
Subject: Re: [PATCH v2 08/10] target/i386/kvm: reset AMD PMU registers
during VM reset
[2] As mentioned in [1], QEMU always sets the vCPU&#
/i386: Introduce Zhaoxin Yongfeng CPU model")
Signed-off-by: Ewan Hai
Reviewed-by: Zhao Liu
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1b64ceaaba..0dd9788a68 100644
--- a/target/i386/cpu.c
+++ b/target/
[2] As mentioned in [1], QEMU always sets the vCPU's vendor to match the host's
vendor
when acceleration (KVM or HVF) is enabled. Therefore, if users want to emulate a
Zhaoxin CPU on an Intel host, the vendor must be set manually.Furthermore,
should we display a warning to users who enable both vP
The model number was mistakenly set to 0x0b (11) in commit ff04bc1ac4.
The correct value is 0x5b. This mistake occurred because the extended
model bits in cpuid[eax=0x1].eax were overlooked, and only the base
model was used.
This patch corrects the model field.
Signed-off-by: Ewan Hai
Thank you for your review!, I will udpate the commit message according
to your suggestions to ensure it provides the most accurate information.
On 8/12/24 05:52, Zhao Liu wrote:
On Fri, Aug 09, 2024 at 05:42:59AM -0400, EwanHai wrote:
Date: Fri, 9 Aug 2024 05:42:59 -0400
From: EwanHai
Subject:
On 8/8/24 23:47, Zhao Liu wrote:
On Thu, Aug 08, 2024 at 11:25:45PM -0400, Ewan Hai wrote:
[snip]
Thank you for your suggestion; the changes will indeed make it clearer.
I have a question: since you’ve already added your reviewed-by tag to
the first three patches, if I want to modify these
On 8/8/24 23:22, Zhao Liu wrote:
Hi EwanHai,
On Thu, Jul 04, 2024 at 07:25:11AM -0400, EwanHai wrote:
Date: Thu, 4 Jul 2024 07:25:11 -0400
From: EwanHai
Subject: [PATCH v2 4/4] target/i386: Update CMPLegacy handling for Zhaoxin
CPUs
X-Mailer: git-send-email 2.34.1
Zhaoxin CPUs handle th
Hi Zhao Liu,
Thank you for your feedback.
On 8/8/24 06:30, Zhao Liu wrote:
Hi EwanHai,
On Thu, Jul 04, 2024 at 07:25:11AM -0400, EwanHai wrote:
Date: Thu, 4 Jul 2024 07:25:11 -0400
From: EwanHai
Subject: [PATCH v2 4/4] target/i386: Update CMPLegacy handling for Zhaoxin
CPUs
X-Mailer: git
Dear Maintainers,
Could you please review the current patchset and let me know if you
have any concerns?
On 7/4/24 07:25, EwanHai wrote:
### Summary of changes
EwanHai (4):
target/i386: Add support for Zhaoxin CPU vendor identification
target/i386: Add CPUID leaf 0xC000_0001 EDX d
Dear Maintainers and Paolo,
I hope this message finds you well. I am writing to inquire about the
status of
the patch I submitted a month ago. Could you please provide any updates or
addtional comments regarding its review?
Thank you for your time and assistance.
Best regards,
Ewan
On 6/25/2
On 7/3/24 23:19, Xiaoyao Li wrote:
On 7/4/2024 11:14 AM, Ewan Hai wrote:
On 7/3/24 10:49, Xiaoyao Li wrote:
On 6/25/2024 5:19 PM, EwanHai wrote:
Zhaoxin and VIA CPUs handle the CMPLegacy bit in the same way
as Intel CPUs. This patch simplifies the existing logic by
using the IS_XXX_CPU
On 7/3/24 10:49, Xiaoyao Li wrote:
On 6/25/2024 5:19 PM, EwanHai wrote:
Zhaoxin and VIA CPUs handle the CMPLegacy bit in the same way
as Intel CPUs. This patch simplifies the existing logic by
using the IS_XXX_CPU macro and includes checks for Zhaoxin
and VIA vendors to align their behavior wit
I’m sorry, but currently Zhaoxin has not released any specs or
datasheets related
to the current patch. Zhaoxin CPUs are compatible with the x86 architecture,
particularly with Intel. For example, you can refer to the Intel SDM
(Software
Developer’s Manual). Regarding the current patch, except f
On 6/25/24 05:49, Zhao Liu wrote:
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 7ad8072748..a7c6c5b2d0 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -2386,6 +2386,7 @@ void kvm_arch_do_init_vcpu(X86CPU *cpu)
static int kvm_get_supported_feature_msrs(KVM
Sorry for my oversight, I am adding the maintainers who were
missed in the previous email.
On 6/24/24 05:58, EwanHai wrote:
Commit 4a910e1 ("target/i386: do not set unsupported VMX secondary
execution controls") implemented a workaround for hosts that have
specific CPUID features but do not supp
Dear Xiaoyao and Maintainers,
Are there any new comments regarding this patch?
On 2/22/24 22:13, Ewan Hai wrote:
On 2/20/24 06:07, Ewan Hai wrote:
On 2/20/24 03:32, Xiaoyao Li wrote:
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 11b8177eff..c8f6c0b531 100644
--- a
On 2/20/24 06:07, Ewan Hai wrote:
On 2/20/24 03:32, Xiaoyao Li wrote:
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 11b8177eff..c8f6c0b531 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -2296,6 +2296,7 @@ void kvm_arch_do_init_vcpu(X86CPU *cpu)
static
On 2/20/24 03:32, Xiaoyao Li wrote:
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 11b8177eff..c8f6c0b531 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -2296,6 +2296,7 @@ void kvm_arch_do_init_vcpu(X86CPU *cpu)
static int kvm_get_supported_feature_msrs(K
Dear QEMU Community,
Two months have passed since my last submission of the patch aimed at
addressing an issue encountered with kernels prior to Linux kernel 5.3.
When using the latest version of QEMU with '-cpu host', if the host
supports the rdseed instruction but not rdseed exiting, it results
rd to hearing from you.
Best regards,
Ewan Hai
On 10/27/23 02:08, Ewan Hai wrote:
Hi Zhao,
since I found last email contains non-plain-text content,
and...@vger.kernel.org
rejected to receive my mail, so just re-send last mail here, to follow
the rule of qemu
/kvm community.
On 10/25/23 23:20, Zha
Hi Zhao,
since I found last email contains non-plain-text content, and...@vger.kernel.org
rejected to receive my mail, so just re-send last mail here, to follow the rule
of qemu
/kvm community.
On 10/25/23 23:20, Zhao Liu wrote:
On Mon, Sep 25, 2023 at 03:14:53AM -0400, EwanHai wrote:
Date: M
On 10/25/23 23:20, Zhao Liu wrote:
On Mon, Sep 25, 2023 at 03:14:53AM -0400, EwanHai wrote:
Date: Mon, 25 Sep 2023 03:14:53 -0400
From: EwanHai
Subject: [PATCH] target/i386/kvm: Refine VMX controls setting for backward
compatibility
X-Mailer: git-send-email 2.34.1
Commit 4a910e1 ("target/i38
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