Dear Maintainers,
Could you please review the current patchset and let me know if you
have any concerns?
On 7/4/24 07:25, EwanHai wrote:
### Summary of changes
EwanHai (4):
target/i386: Add support for Zhaoxin CPU vendor identification
target/i386: Add CPUID leaf 0xC000_0001 EDX definitions
target/i386: Introduce Zhaoxin Yongfeng CPU model
target/i386: Update CMPLegacy handling for Zhaoxin CPUs
target/i386/cpu.c | 128 ++++++++++++++++++++++++++++++++++++++++++++--
target/i386/cpu.h | 41 ++++++++++++++-
2 files changed, 165 insertions(+), 4 deletions(-)
### Changes since v1
1. Removed VIA-related information from the patch description to avoid
misunderstanding.
2. Replaced CPUID_VENDOR_VIA with CPUID_VENDOR_ZHAOXIN1 because the
"Centaurhauls" vendor ID now belongs to Zhaoxin.The previous CPUID_VENDOR_VIA
macro was only defined but never used in QEMU, making this change
straightforward.
v1 link: https://lore.kernel.org/qemu-devel/20240625091905.1325205-1-ewanhai-
o...@zhaoxin.com/
### Known Issues
1. Issue with VMX Preemption Timer Rate on Yongfeng CPU:
- Description: On Yongfeng CPUs, the VMX preemption timer rate is 128,
meaning that bits 4:0 of MSR_IA32_VMX_MISC_CTLS should be set to 7.
However, due to Intel's rate being 5, the Linux kernel has hardcoded
this value as 5: `#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5`.
- Impact: This discrepancy can cause incorrect behavior in the VMX
preemption timer on Yongfeng CPUs.
- Workaround: A patch to correct this issue in the Linux kernel is
currently being prepared and will be submitted soon.
