This will help developers of ATS-capable devices to track a state.
Signed-off-by: Clement Mathieu--Drif
---
include/system/memory.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/system/memory.h b/include/system/memory.h
index fbbf4cf911..fc35a0dcad 100644
--- a/include/system
This is meant to be used by ATS-capable devices.
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pci.c | 17 +
include/hw/pci/pci.h | 33 +
2 files changed, 50 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index fc4954ac81
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 25 +
include/hw/pci/pcie.h | 6 +-
include/hw/pci/pcie_regs.h | 5 +
3 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 1b12db6fa2
- PRI
- Device IOTLB invalidations
- Requests with already pre-translated addresses
- A demo device
- A simple driver for the demo device
- A userspace program (for testing and demonstration purposes)
https://github.com/BullSequana/Qemu-in-guest-SVM-demo
Clement Mathi
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 26 ++
include/hw/pci/pcie.h | 5 -
include/hw/pci/pcie_regs.h | 3 +++
3 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 36de709801
Devices implementing ATS can send translation requests using
pci_ats_request_translation. The invalidation events are sent
back to the device using the iommu notifier managed with
pci_iommu_register_iotlb_notifier / pci_iommu_unregister_iotlb_notifier.
Signed-off-by: Clement Mathieu--Drif
Co
pasid_enabled checks whether the capability is
present or not. If so, we read the configuration space to get
the status of the feature (enabled or not).
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 9 +
include/hw/pci/pcie.h | 2 ++
2 files changed, 11 insertions
The cached is_master value is necessary to know if a device is
allowed to issue ATS/PRI requests or not as these operations do not go
through the master_enable memory region.
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pci.c| 23 +--
include/hw/pci
This kind of information is needed by devices implementing ATS in order
to initialize their translation cache.
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pci.c | 17 +
include/hw/pci/pci.h | 26 ++
2 files changed, 43 insertions(+)
diff
A device can send a PRI request to the IOMMU using pci_pri_request_page.
The PRI response is sent back using the notifier managed with
pci_pri_register_notifier and pci_pri_unregister_notifier.
Signed-off-by: Clement Mathieu--Drif
Co-authored-by: Ethan Milon
---
hw/pci/pci.c | 66
pri_enabled can be used to check whether the capability is present and
enabled on a PCIe device
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 9 +
include/hw/pci/pcie.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index
ats_enabled checks whether the capability is
present or not. If so, we read the configuration space to get
the status of the feature (enabled or not).
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 9 +
include/hw/pci/pcie.h | 1 +
2 files changed, 10 insertions
On 14/05/2025 9:36 am, Michael S. Tsirkin wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> On Thu, Feb 27, 2025 at 10:54:47AM +, CLEMENT MATHIEU--DRIF wrote:
&
On 14/05/2025 1:48 pm, Michael S. Tsirkin wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> On Wed, Apr 30, 2025 at 12:48:06PM +, CLEMENT MATHIEU--DRIF wrote:
>
Cc'ing Paolo
On 30/04/2025 2:48 pm, CLEMENT MATHIEU--DRIF wrote:
> This series introduces 2 fixes and improves locking style
> consistency in the VT-d device.
>
> Changes since v4:
> - Re-check if the address space is present once both bql and
> iommu lock ar
On 29/04/2025 8:01 am, Duan, Zhenzhong wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
>> -Original Message-
>> From: CLEMENT MATHIEU--DRIF
>&
-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index dad1d9f300..144e25622a 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -4205,9
vtd_switch_address_space needs to take the BQL if not already held.
Use BQL_LOCK_GUARD to make the iommu implementation more consistent.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/hw/i386
This series introduces 2 fixes and improves locking style
consistency in the VT-d device.
Changes since v4:
- Re-check if the address space is present once both bql and
iommu lock are held.
Clement Mathieu--Drif (2):
intel_iommu: Use BQL_LOCK_GUARD to manage cleanup
Hi Zhenzhong,
On 28/04/2025 10:55 am, Duan, Zhenzhong wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Hi Clement,
>
>> -Original Message-
>&g
Address space creation might end up being called without holding the
bql as it is exposed through the IOMMU ops.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index
vtd_switch_address_space needs to take the BQL if not already held.
Use BQL_LOCK_GUARD to make the iommu implementation more consistent.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/hw/i386
vtd_find_add_as can be called by multiple threads which leads to a race
condition on address space creation. The IOMMU lock must be taken to
avoid such a race.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 28 ++--
1 file changed, 26 insertions(+), 2
This series introduces 2 fixes and improves locking style
consistency in the VT-d device.
Clement Mathieu--Drif (3):
intel_iommu: Take the bql before registering a new address space
intel_iommu: Use BQL_LOCK_GUARD to manage cleanup automatically
intel_iommu: Take the VTD lock when looking
On 23/04/2025 12:06 pm, Michael S. Tsirkin wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> On Wed, Apr 23, 2025 at 09:15:36AM +, CLEMENT MATHIEU--DRIF wrote:
&g
On 23/04/2025 8:00 am, Michael S. Tsirkin wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> On Wed, Apr 23, 2025 at 05:38:20AM +, CLEMENT MATHIEU--DRIF wrote:
&
vtd_switch_address_space needs to take the BQL if not already held.
Use BQL_LOCK_GUARD to make the iommu implementation more consistent.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/hw/i386
Address space creation might end up being called without holding the
bql as it is exposed through the IOMMU ops.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index
On 17/04/2025 5:27 pm, Alejandro Jimenez wrote:
> Caution: External email. Do not open attachments or click links, unless
> this email comes from a known sender and you know the content is safe.
>
>
> On 4/17/25 8:40 AM, CLEMENT MATHIEU--DRIF wrote:
>>
>>
>>
On 14/04/2025 4:02 am, Alejandro Jimenez wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> The current amdvi_page_walk() is designed to be called by the replay()
> method. Rather than
On 15/04/2025 8:53 am, Philippe Mathieu-Daudé wrote:
> Caution: External email. Do not open attachments or click links, unless
> this email comes from a known sender and you know the content is safe.
>
>
> On 15/4/25 08:18, CLEMENT MATHIEU--DRIF wrote:
>> Address space
Address space creation might end up being called without holding the
bql as it is exposed through the IOMMU ops.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index
Bonzini wrote:
>>> On Tue, Apr 15, 2025 at 1:51 PM CLEMENT MATHIEU--DRIF
>>> wrote:
>>>> On 15/04/2025 11:30 am, Paolo Bonzini wrote:
>>>>> Caution: External email. Do not open attachments or click links,
>>>>> unless
>>>>&g
On 15/04/2025 2:33 pm, Stefan Hajnoczi wrote:
> On Tue, Apr 15, 2025 at 03:11:00AM -0400, Michael S. Tsirkin wrote:
>> On Tue, Apr 15, 2025 at 06:18:08AM +, CLEMENT MATHIEU--DRIF wrote:
>>> Address space creation might end up being called without holding the
>>> b
On 15/04/2025 11:30 am, Paolo Bonzini wrote:
> Caution: External email. Do not open attachments or click links, unless
> this email comes from a known sender and you know the content is safe.
>
>
> On 4/15/25 08:18, CLEMENT MATHIEU--DRIF wrote:
>> Address space creati
Address space creation might end up being called without holding the
bql as it is exposed through the IOMMU ops.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index
Reviewed-by: Clement Mathieu--Drif
On 09/04/2025 4:36 am, Bibo Mao wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Macro PCH_PIC_HTMSI_VEC_OFFSET and PCH_PIC_ROUTE_
Reviewed-by: Clement Mathieu--Drif
On 09/04/2025 4:36 am, Bibo Mao wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> For some registers with width 8 bytes, its name is
On 12/03/2025 13:54, Yi Liu wrote:
> Caution: External email. Do not open attachments or click links, unless
> this email comes from a known sender and you know the content is safe.
>
>
> On 2025/3/12 18:03, Philippe Mathieu-Daudé wrote:
>> Hi Markus,
>>
>> (Cc'ing Yi, Clément and Zhenzhong fo
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
tests/unit/meson.build | 1 +
tests/unit/test-atc.c | 527 +
2 files changed, 528 insertions(+)
create mode 100644 tests/unit/test-atc.c
diff --git a/tests/unit/meson.build b/tests
From: Clement Mathieu--Drif
pasid_enabled checks whether the capability is
present or not. If so, we read the configuration space to get
the status of the feature (enabled or not).
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 9 +
include/hw/pci/pcie.h | 2 ++
2
From: Clement Mathieu--Drif
This will be useful for devices that support ATS
and need to store entries in an ATC (device IOTLB).
Signed-off-by: Clement Mathieu--Drif
---
include/exec/memory.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 17 -
include/hw/i386/intel_iommu.h | 2 +-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index a360119fbe
From: Clement Mathieu--Drif
Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5.
This is needed by devices that support ATS.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw
From: Clement Mathieu--Drif
This patch set belongs to a list of series that add SVM support for VT-d.
Here we focus on implementing ATS support in the IOMMU and adding a
PCI-level API to be used by virtual devices.
This work is based on the VT-d specification version 4.1 (March 2023).
Here is
From: Clement Mathieu--Drif
PSS field of the ecap register stores the supported PASID size minus 1.
Thus, this commit adds support for 20bits PASIDs.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 2 +-
hw/i386/intel_iommu_internal.h | 1 +
2 files changed, 2
From: Clement Mathieu--Drif
The cached is_master value is necessary to know if a device is
allowed to issue ATS requests or not.
This behavior is implemented in an upcoming patch.
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pci.c| 25 +++--
include/hw
From: Clement Mathieu--Drif
The region returned by this operation will be used as the input region
for ATS.
Signed-off-by: Clement Mathieu--Drif
---
include/hw/pci/pci.h | 16
1 file changed, 16 insertions(+)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index
From: Clement Mathieu--Drif
PASID value must be used by devices as a key (or part of a key)
when populating their ATC with the IOTLB entries returned by the IOMMU.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/i386
From: Clement Mathieu--Drif
As the SVM-capable devices will need to cache translations, we provide
an first implementation.
This cache uses a two-level design based on hash tables.
The first level is indexed by a PASID and the second by a virtual addresse.
Signed-off-by: Clement Mathieu--Drif
From: Clement Mathieu--Drif
Devices implementing ATS can send translation requests using
pci_ats_request_translation_pasid.
The invalidation events are sent back to the device using the iommu
notifier managed with pci_register_iommu_tlb_event_notifier and
pci_unregister_iommu_tlb_event_notifier
From: Clement Mathieu--Drif
This will help developers of svm devices to track a state
Signed-off-by: Clement Mathieu--Drif
---
include/exec/memory.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index eee625a9c6..4d240cad1c 100644
--- a
From: Clement Mathieu--Drif
We use this information in vtd_do_iommu_translate to populate the
IOMMUTLBEntry and indicate the correct page mask. This prevents ATS
devices from sending many useless translation requests when a megapage
or gigapage iova is not mapped to a physical address.
Signed
From: Clement Mathieu--Drif
IOMMU have to implement iommu_ats_request_translation to support ATS.
Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb
entries returned by a translation request.
We decided not to use the existing translation operation for 2 reasons.
First, ATS is
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 74 --
hw/i386/intel_iommu_internal.h | 1 +
2 files changed, 72 insertions(+), 3 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 24
include/hw/pci/pcie.h | 6 +-
include/hw/pci/pcie_regs.h | 5 +
3 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pcie.c b/hw/pci
From: Clement Mathieu--Drif
ats_enabled checks whether the capability is
present or not. If so, we read the configuration space to get
the status of the feature (enabled or not).
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 9 +
include/hw/pci/pcie.h | 1 +
2 files
From: Clement Mathieu--Drif
We add a convenient way to initialize an device-iotlb notifier.
This is meant to be used by ATS-capable devices.
pci_device_iommu_memory_region_pasid is introduces in this commit and
will be used in several other SVM-related functions exposed in
the PCI API.
Signed
From: Clement Mathieu--Drif
This will be necessary for devices implementing ATS.
We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to
IOMMU_ACCESS_FLAG to support more access flags.
IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility.
Here are the flags added
On 21/02/2025 11:57, Michael S. Tsirkin wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> On Fri, Feb 21, 2025 at 08:07:25AM +, CLEMENT MATHIEU--DRIF wrote:
&
From: Clement Mathieu--Drif
Devices implementing ATS can send translation requests using
pci_ats_request_translation_pasid.
The invalidation events are sent back to the device using the iommu
notifier managed with pci_register_iommu_tlb_event_notifier and
pci_unregister_iommu_tlb_event_notifier
From: Clement Mathieu--Drif
ats_enabled checks whether the capability is
present or not. If so, we read the configuration space to get
the status of the feature (enabled or not).
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 9 +
include/hw/pci/pcie.h | 1 +
2 files
From: Clement Mathieu--Drif
The region returned by this operation will be used as the input region
for ATS.
Signed-off-by: Clement Mathieu--Drif
---
include/hw/pci/pci.h | 16
1 file changed, 16 insertions(+)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index
From: Clement Mathieu--Drif
This will help developers of svm devices to track a state
Signed-off-by: Clement Mathieu--Drif
---
include/exec/memory.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index eee625a9c6..4d240cad1c 100644
--- a
From: Clement Mathieu--Drif
PSS field of the ecap register stores the supported PASID size minus 1.
Thus, this commit adds support for 20bits PASIDs.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 2 +-
hw/i386/intel_iommu_internal.h | 1 +
2 files changed, 2
From: Clement Mathieu--Drif
IOMMU have to implement iommu_ats_request_translation to support ATS.
Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb
entries returned by a translation request.
We decided not to use the existing translation operation for 2 reasons.
First, ATS is
From: Clement Mathieu--Drif
pasid_enabled checks whether the capability is
present or not. If so, we read the configuration space to get
the status of the feature (enabled or not).
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 9 +
include/hw/pci/pcie.h | 2 ++
2
From: Clement Mathieu--Drif
Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5.
This is needed by devices that support ATS.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw
From: Clement Mathieu--Drif
We use this information in vtd_do_iommu_translate to populate the
IOMMUTLBEntry and indicate the correct page mask. This prevents ATS
devices from sending many useless translation requests when a megapage
or gigapage iova is not mapped to a physical address.
Signed
From: Clement Mathieu--Drif
The cached is_master value is necessary to know if a device is
allowed to issue ATS requests or not.
This behavior is implemented in an upcoming patch.
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pci.c| 25 +++--
include/hw
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 24
include/hw/pci/pcie.h | 6 +-
include/hw/pci/pcie_regs.h | 5 +
3 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pcie.c b/hw/pci
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 17 -
include/hw/i386/intel_iommu.h | 2 +-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index a360119fbe
From: Clement Mathieu--Drif
This patch set belongs to a list of series that add SVM support for VT-d.
Here we focus on implementing ATS support in the IOMMU and adding a
PCI-level API to be used by virtual devices.
This work is based on the VT-d specification version 4.1 (March 2023).
Here is
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
tests/unit/meson.build | 1 +
tests/unit/test-atc.c | 527 +
2 files changed, 528 insertions(+)
create mode 100644 tests/unit/test-atc.c
diff --git a/tests/unit/meson.build b/tests
From: Clement Mathieu--Drif
We add a convenient way to initialize an device-iotlb notifier.
This is meant to be used by ATS-capable devices.
pci_device_iommu_memory_region_pasid is introduces in this commit and
will be used in several other SVM-related functions exposed in
the PCI API.
Signed
From: Clement Mathieu--Drif
As the SVM-capable devices will need to cache translations, we provide
an first implementation.
This cache uses a two-level design based on hash tables.
The first level is indexed by a PASID and the second by a virtual addresse.
Signed-off-by: Clement Mathieu--Drif
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 74 --
hw/i386/intel_iommu_internal.h | 1 +
2 files changed, 72 insertions(+), 3 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
From: Clement Mathieu--Drif
This will be necessary for devices implementing ATS.
We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to
IOMMU_ACCESS_FLAG to support more access flags.
IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility.
Here are the flags added
From: Clement Mathieu--Drif
PASID value must be used by devices as a key (or part of a key)
when populating their ATC with the IOTLB entries returned by the IOMMU.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/i386
From: Clement Mathieu--Drif
This will be useful for devices that support ATS
and need to store entries in an ATC (device IOTLB).
Signed-off-by: Clement Mathieu--Drif
---
include/exec/memory.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
On 20/02/2025 22:13, Michael S. Tsirkin wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> On Mon, Jan 20, 2025 at 05:41:32PM +, CLEMENT MATHIEU--DRIF wrote:
&
Reviewed-by: Clément Mathieu--Drif
On 19/02/2025 09:22, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> In early days vtd_ce_get_rid2pasid_entry() is used to get pasid
Kindly ping
Thanks everyone
>cmd
On 20/01/2025 18:41, CLEMENT MATHIEU--DRIF wrote:
> From: Clement Mathieu--Drif
>
> This patch set belongs to a list of series that add SVM support for VT-d.
>
> Here we focus on implementing ATS support in the IOMMU and adding a
> PCI-le
Reviewed-by: Clément Mathieu--Drif
On 25/01/2025 19:13, Philippe Mathieu-Daudé wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> When multiple QOM types are registered in the same file,
Reviewed-by: Clément Mathieu--Drif
On 25/01/2025 19:13, Philippe Mathieu-Daudé wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Because the network eTSEC device can be optionally plugg
Reviewed-by: Clément Mathieu--Drif
On 25/01/2025 19:13, Philippe Mathieu-Daudé wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Rather than using the obscure system_bus_info.instance_s
Reviewed-by: Clément Mathieu--Drif
On 25/01/2025 19:13, Philippe Mathieu-Daudé wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Some TYPE_SYS_BUS_DEVICEs can be optionally dynamically
Reviewed-by: Clément Mathieu--Drif
On 25/01/2025 19:13, Philippe Mathieu-Daudé wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Because the RAM FB device can be optionally plugged on
Reviewed-by: Clément Mathieu--Drif
On 25/01/2025 19:13, Philippe Mathieu-Daudé wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Because the TPM TIS sysbus device can be optionally plug
Reviewed-by: Clément Mathieu--Drif
Thanks phil
On 25/01/2025 19:13, Philippe Mathieu-Daudé wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Do not explain why _X86_IOMMU devices are u
From: Clement Mathieu--Drif
Devices implementing ATS can send translation requests using
pci_ats_request_translation_pasid.
The invalidation events are sent back to the device using the iommu
notifier managed with pci_register_iommu_tlb_event_notifier and
pci_unregister_iommu_tlb_event_notifier
From: Clement Mathieu--Drif
This will help developers of svm devices to track a state
Signed-off-by: Clement Mathieu--Drif
---
include/exec/memory.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 9889b97abb..468b003bf1 100644
--- a
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 24
include/hw/pci/pcie.h | 6 +-
include/hw/pci/pcie_regs.h | 5 +
3 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pcie.c b/hw/pci
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
tests/unit/meson.build | 1 +
tests/unit/test-atc.c | 527 +
2 files changed, 528 insertions(+)
create mode 100644 tests/unit/test-atc.c
diff --git a/tests/unit/meson.build b/tests
From: Clement Mathieu--Drif
ats_enabled checks whether the capability is
present or not. If so, we read the configuration space to get
the status of the feature (enabled or not).
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 9 +
include/hw/pci/pcie.h | 1 +
2 files
From: Clement Mathieu--Drif
PSS field of the ecap register stores the supported PASID size minus 1.
Thus, this commit adds support for 20bits PASIDs.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 2 +-
hw/i386/intel_iommu_internal.h | 1 +
2 files changed, 2
From: Clement Mathieu--Drif
pasid_enabled checks whether the capability is
present or not. If so, we read the configuration space to get
the status of the feature (enabled or not).
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 9 +
include/hw/pci/pcie.h | 2 ++
2
From: Clement Mathieu--Drif
PASID value must be used by devices as a key (or part of a key)
when populating their ATC with the IOTLB entries returned by the IOMMU.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/i386
From: Clement Mathieu--Drif
The region returned by this operation will be used as the input region
for ATS.
Signed-off-by: Clement Mathieu--Drif
---
include/hw/pci/pci.h | 16
1 file changed, 16 insertions(+)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index
From: Clement Mathieu--Drif
We use this information in vtd_do_iommu_translate to populate the
IOMMUTLBEntry and indicate the correct page mask. This prevents ATS
devices from sending many useless translation requests when a megapage
or gigapage iova is not mapped to a physical address.
Signed
1 - 100 of 417 matches
Mail list logo
