be rebased on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
I applied the first 6 patches as they apply cleanly
Alistair
>
> v5: Improvements based on Richard Henderson's feedback.
> - Fixed code gen logic to use gen_update_pc() instead of
> tcg_constant_tl().
&
On Thu, Dec 5, 2024 at 9:36 PM Rajnesh Kanwal wrote:
>
> Add a subsection to machine.c to migrate CTR CSR state
>
> Signed-off-by: Rajnesh Kanwal
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/machine.c | 25 +
> 1 file changed, 25 i
e),
> +MULTI_EXT_CFG_BOOL("smctr", ext_smctr, false),
> +MULTI_EXT_CFG_BOOL("ssctr", ext_ssctr, false),
This should be the very last patch (once everything is supported)
Otherwise
Acked-by: Alistair Francis
Alistair
> MULTI_EXT_CFG_BOO
On Thu, Dec 5, 2024 at 9:35 PM Rajnesh Kanwal wrote:
>
> CTR extension adds a new instruction sctrclr to quickly
> clear the recorded entries buffer.
>
> Signed-off-by: Rajnesh Kanwal
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h
t
> exceptions and counter overflow interrupts.
>
> Signed-off-by: Rajnesh Kanwal
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 7 +
> target/riscv/cpu_helper.c | 259
> +++
t(env, RVC) && (retpc & 0x3)) {
> -riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> +if (!riscv_has_ext(env, RVC) && !env_archcpu(env)->cfg.ext_zca) {
I think you can just check ext_zca, as misa.C enables ext_zca
Alistair
> +
On Thu, Dec 5, 2024 at 9:36 PM Rajnesh Kanwal wrote:
>
> This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and
> sctrdepth CSRs handling.
>
> Signed-off-by: Rajnesh Kanwal
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 5 ++
> targ
On Tue, Jan 28, 2025 at 4:05 PM Alistair Francis wrote:
>
> Bin Meng has been a long time contributor and maintainer for QEMU RISC-V
> and has been very beneficial to the RISC-V ecosystem.
>
> Unfortunately his email has started to bounce so this patch is removing
> them from
> Reviewed-by: Andrew Jones
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> hw/riscv/virt.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 2bc5a9dd98..fb1928cebf 100644
> --- a/hw/riscv/virt.c
> +++ b/
askovitis
> Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 2bc5a9dd98..fb1928cebf 100644
> --- a/hw/riscv/virt.c
> +++ b/
;).
>
> Migrate the tick_offset directly, adding it as a version-dependent field
> to VMState. Keep the old behavior when migrating from previous versions.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2033
> Signed-off-by: Rodrigo Dias Correa
Thanks!
Applied to
e too much though?
We probably don't need to document the register names
Alistair
> I left the door somewhat open on this via the NAME_NUMBER format.
>
> There was some checking logic where if data is supplied then it forces
> a check for data-len.
> I could relax that check
r for multiple patches in the future:
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#include-a-meaningful-cover-letter
Thanks!
Applied to riscv-to-apply.next
Alistair
>> ---
>> hw/riscv/riscv-iommu.h | 5 -
>> 1 file changed, 5 deletions(-)
>>
>> diff
On Thu, Jan 16, 2025 at 4:44 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This new version has tweaks suggested by Drew in v3. No major changes
> were made.
>
> Patches based on alistair/riscv-to-apply.next.
>
> All patches acked.
>
> Changes from v3:
> - patc
On Thu, Jan 16, 2025 at 12:18 AM Jason Chien wrote:
>
> The header contains duplicate macro definitions.
> This commit eliminates the duplicate part.
>
> Signed-off-by: Jason Chien
> Reviewed-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
Reviewed-by: Alista
RFC label.
> v7:
>- Fix build errors, add Reviewed-by, Acked-by.
> ---
>
> Ivan Klokov (2):
> target/riscv: Add RISC-V CSR qtest support
> tests/qtest: QTest example for RISC-V CSR register
Do you mind rebasing on
https://github.com/alistair23/qemu/tree/riscv-to-ap
;).
>
> Migrate the tick_offset directly, adding it as a version-dependent field
> to VMState. Keep the old behavior when migrating from previous versions.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2033
> Signed-off-by: Rodrigo Dias Correa
Reviewed-by: Alistai
3 only.
>
> A new "rva23u64" CPU is also added.
>
> [1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Alistair
> ---
> target
anging the past, change the priv_ver check now to allow
> profiles to run in a newer priv_ver. This universe will have one less
> warning to deal with.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Alistair
> --
t;hw/riscv: add RISC-V IOMMU base emulation").
>
> Signed-off-by: Jason Chien
> Reviewed-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/riscv-iommu.h | 5 -
> 1 file changed, 5 deletions(-)
>
riscv-profiles/blob/main/src/rva23-profile.adoc
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 39 +++
&g
hange does nothing for the existing profiles but will make RVA23S64
> simpler.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 6 --
>
aim
> support for it.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c| 1 +
> tests/data/acpi/riscv64/virt/RHCT | Bin 390 -> 398 bytes
> 2 files changed, 1
v/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23u64-profile
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c| 2 +-
> tests/data/acpi/riscv64/virt/RHCT | Bin 398
riscv-profiles/blob/main/src/rva23-profile.adoc#rva23u64-profile
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c| 2 +-
> tests/data/acpi/riscv64/virt/RHCT | Bin 398 -> 400 bytes
> 2 files
riginal "hart_idx" parameter should be used for logging to
> ensure accuracy, rather than the masked value.
>
> Signed-off-by: Huang Borong
> Reviewed-by: Daniel Henrique Barboza
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> hw/intc/riscv_aplic
: use wp size = 4 for 32-bit CPUs
> target/riscv: throw debug exception before page fault
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu_helper.c | 18 ++
> target/riscv/debug.c | 6 --
> 2 files changed, 22 insertions(+), 2 deletions(-)
>
> --
> 2.47.1
>
>
pu_check_watchpoint()
> will return and we'll fall-through the regular path to
> raise_mmu_exception().
>
> [1] https://gitlab.com/qemu-project/qemu/-/issues/2627
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2627
> Signed-off-by: Daniel Henrique Barboza
Revie
>
> At this moment we're using def_size = 8 regardless of CPU XLEN. Use
> def_size = 4 in case we're running 32 bits.
>
> Fixes: 95799e36c1 ("target/riscv: Add initial support for the Sdtrig
> extension")
> Signed-off-by: Daniel Henrique Barboza
Reviewed-b
vlen is
> 1024(vlenb=128).
>
> Signed-off-by: Max Chou
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3d4bd157d2
hould be updated when vl is larger than 0.
>
> Signed-off-by: Max Chou
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/vector_helper.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/v
sa) Register".
>
> Signed-off-by: Evgenii Prokopiev
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/csr.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index eab8e50012..fca2b1b40f 100644
sa) Register".
>
> Signed-off-by: Evgenii Prokopiev
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/csr.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index eab8e50012..fca2b1b40f 100644
3 only.
>
> A new "rva23u64" CPU is also added.
>
> [1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu-qom.h | 1 +
> target/risc
To make a better use of the label, remove the 'else' from the
> xiselect_aia_range() chain and let it fall-through to the 'done' label
> since they are now both returning RISCV_EXCP_ILLEGAL_INST.
>
> Resolves: Coverity CID 1590356
> Fixes: dc0280723d ("target/
aim
> support for it.
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c| 1 +
> tests/data/acpi/riscv64/virt/RHCT | Bin 390 -> 398 bytes
> 2 files changed, 1 insertion(+)
>
> diff
aia_smode32()
> target/riscv/cpu_helper.c: fix bad_shift in riscv_cpu_interrupt()
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu_helper.c | 4 +++-
> target/riscv/csr.c| 24 +++-
> 2 files changed, 6 insertions(+), 22 deletions(-)
>
> --
> 2.47.1
>
>
64' guard like
> 'mode' is already doing right before 'vsmode_exc'.
>
> Resolves: Coverity CID 1590355
> Fixes: 967760f62c ("target/riscv: Implement Ssdbltrp exception handling")
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Fra
> return ret;
> }
>
> if (ret != RISCV_EXCP_NONE) {
> return ret;
> }
>
> Remove the duplication to fix the deadcode.
>
> Resolves: Coverity CID 1590358
> Fixes: dbcb6e1ccf ("target/riscv: Enable S*stateen bits for AIA")
> Signed-off-by:
gt; goto done;
> }
>
> return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask);
>
> done:
> return RISCV_EXCP_ILLEGAL_INST;
>
> Which we will eliminate it and just do 'return RISCV_EXCP_ILLEGAL_INST'
> instead.
>
> Resolves: Coverity C
CP_NONE;
>
> The flag 'virt' is now unused. Remove it.
>
> Fix the 'goto done' identation while we're at it.
>
> Resolves: Coverity CID 1590359
> Fixes: dc0280723d ("target/riscv: Decouple AIA processing from xiselect and
> xireg")
> Sign
case, mhpmevent value should have zero in lower 56 bits.
> Software may set the OF bit to indicate disable interrupt.
>
> Ensure that correct value is checked after masking while clearing the
> event encodings.
>
> Signed-off-by: Atish Patra
Acked-by: Alistair Francis
Alistair
t; +++ b/target/riscv/cpu_bits.h
> @@ -9,6 +9,10 @@
> (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
> (uint64_t)(mask)))
>
> +#ifndef GENMASK_ULL
> +#define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l))
> +
On Tue, Jan 28, 2025 at 4:05 PM Alistair Francis wrote:
>
> Bin Meng has been a long time contributor and maintainer for QEMU RISC-V
> and has been very beneficial to the RISC-V ecosystem.
>
> Unfortunately his email has started to bounce so this patch is removing
> them from
.
Note that I'm not removing Bin Meng as a "SD (Secure Card)" maintainer.
Signed-off-by: Alistair Francis
---
MAINTAINERS | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7be3d8f431..a0e305aa99 100644
--- a/MAINTAINERS
+++ b/MAINTA
On Mon, Jan 27, 2025 at 9:39 PM Philippe Mathieu-Daudé
wrote:
>
> Last use of load_elf_ram() was removed in commit 188e255bf8e
> ("hw/s390x: Remove the possibility to load the s390-netboot.img
> binary"), remove it.
>
> Signed-off-by: Philippe Mathieu-Daudé
R
From: Atish Patra
The dependant ISA features are enabled at the end of cpu_realize
in finalize_features. Thus, PMU init should be invoked after that
only. Move the init invocation to riscv_tcg_cpu_finalize_features.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-ID
extension is enabled.
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Signed-off-by: Atish Patra
Message-ID: <20250110-counter_delegation-v5-10-e83d797ae...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 12 +++-
1 file changed, 11 insertions
: Craig Blackmore
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Message-ID: <20241218142353.1027938-3-craig.blackm...@embecosm.com>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c | 16
1 file changed, 16 insertions(+)
diff --git a/
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
Message-ID: <20250106054336.1878291-3-frank.ch...@sifive.com>
Sign
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
Message-ID: <20250106054336.1878291-2-frank.ch...@sifive.com>
Signed-off-by:
disable
it for the max cpu to avoid breaking regression tests.
Signed-off-by: Clément Léger
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20250116131539.2475785-1-cle...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 ++
target/riscv/tcg/tcg-cpu.
the functionality to handle the RNMI signals.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20250106054336.1878291-4-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
include/hw/riscv/riscv_ha
with
the same PSCID, but only the former one should be invalidated.
Signed-off-by: Jason Chien
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20241108110147.11178-1-jason.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
hw/riscv/riscv-iommu.c
: Alistair Francis
Message-ID: <20250110125441.3208676-4-cle...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/op_helper.c | 35 ++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
From: Clément Léger
Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT,
{H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the
presence of the Ssdbltrp ISA extension.
Signed-off-by: Clément Léger
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message
From: Kaiwen Xue
Since xiselect and xireg also will be of use in sxcsrind, AIA should
have its own separated interface when those CSRs are accessed.
Signed-off-by: Kaiwen Xue
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-ID: <20250110-counter_delegation-v5-2-e83d79
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-ID: <20250116223609.81594-1-phi...@linaro.org>
Signed-off-by: Alistair Francis
---
hw/char/riscv_htif.c | 15 +++
hw/char/trace-events | 4
2 files changed, 7 inse
From: Clément Léger
When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared
when executing sret if executed in M-mode. When executing mret/mnret,
SSTATUS.MDT is cleared.
Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
Message-ID: <20250110125441.3208676-8-
From: Kaiwen Xue
This adds checks in ops performed on xireg and xireg2-xireg6 so that the
counter delegation function will receive a valid xiselect value with the
proper extensions enabled.
Co-developed-by: Atish Patra
Signed-off-by: Kaiwen Xue
Reviewed-by: Alistair Francis
Signed-off-by
: <20250113194410.1307494-1-baturo.ale...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 2 ++
target/riscv/cpu.c | 23 +++
2 files changed, 25 insertions(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index aef896ba00..b410
From: Clément Léger
When the Smsdbltrp ISA extension is enabled, if a trap happens while
MSTATUS.MDT is already set, it will trigger an abort or an NMI is the
Smrnmi extension is available.
Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
Message-ID: <20250110125441.3208676-9-
From: Kaiwen Xue
This adds definitions for counter delegation, including the new
scountinhibit register and the mstateen.CD bit.
Signed-off-by: Kaiwen Xue
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-ID: <20250110-counter_delegation-v5-6-e83d797ae...@rivosinc.com>
From: Clément Léger
When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode
while SSTATUS.SDT isn't cleared, generate a double trap exception to
M-mode.
Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
Message-ID: <20250110125441.3208676-5-cle...@rivosinc.com
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Signed-off-by: Atish Patra
Message-ID: <20250110-counter_delegation-v5-8-e83d797ae...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 304 +++--
1 file changed, 292 inse
From: Atish Patra
This adds the properties for counter delegation ISA extensions
(Smcdeleg/Ssccfg). Definitions of new registers and and implementation
will come in the next set of patches.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message
From: Clément Léger
Add the switch to enable the Ssdbltrp ISA extension.
Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
Message-ID: <20250110125441.3208676-6-cle...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
to RISCVException in
generate_exception() to guarantee that all callers of
riscv_raise_exception() will use the enum.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250106173734.412353-2-dbarb...@ventanamicro.com>
Signe
ing henvcfg upper part when writing it
with write_henvcfgh().
Signed-off-by: Clément Léger
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20250110125441.3208676-2-cle...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 10 -
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Message-ID: <20250106102346.1100149-8-baturo.ale...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target
corresponding
checks in the CSR accessor functions.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-ID: <20250110-counter_delegation-v5-3-e83d797ae...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 85 +-
1 file c
MNPELP if yLPE is 1;
otherwise, it is set to NO_LP_EXPECTED.
Signed-off-by: Frank Chang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20250106054336.1878291-7-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 1 +
From: Atish Patra
Add configuration options so that they can be enabled/disabld from
qemu commandline.
Acked-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Atish Patra
Message-ID: <20250110-counter_delegation-v5-11-e83d797ae...@rivosinc.com>
Signed-off-by: Al
uro
Acked-by: Alistair Francis
Message-ID: <20250106102346.1100149-2-baturo.ale...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 33 +---
target/riscv/cpu_bits.h | 87 --
target/riscv/cpu.c | 13 +-
target/riscv/cpu_helper.c| 5
Reviewed-by: Alistair Francis
Message-ID: <20241218114026.1652352-6-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c| 1 +
tests/data/acpi/riscv64/virt/RHCT | Bin 356 -> 364 bytes
2 files changed, 1 insertion(+)
diff --git a/target/r
Signed-off-by: Tommy Wu
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20250106054336.1878291-5-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 1 +
target/riscv/insn32.decode
From: Clément Léger
Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior.
Also set MDT to 1 at reset according to the specification.
Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
Message-ID: <20250110125441.3208676-7-cle...@rivosinc.com>
Signed-off-by: Al
.
Co-developed-by: Atish Patra
Signed-off-by: Kaiwen Xue
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Signed-off-by: Atish Patra
Message-ID: <20250110-counter_delegation-v5-4-e83d797ae...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20250106102346.1100149-7-baturo.ale...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 1 +
target/riscv/internals.h
From: Daniel Henrique Barboza
shvsatpa is defined in RVA22 as:
"All translation modes supported in satp must be supported in vsatp."
This is always true in TCG so let's claim support for it.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Fran
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20250106102346.1100149-4-baturo.ale...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 5 +++
target/riscv/cpu_helper.
];
...
} s;
Directly use that instead of the &first_cpu global.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-ID: <20250112231344.34632-3-phi...@linaro.org>
Signed-off-by: Alistair Francis
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+),
From: Kaiwen Xue
This adds the properties for sxcsrind. Definitions of new registers and
implementations will come with future patches.
Signed-off-by: Kaiwen Xue
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Signed-off-by: Atish Patra
Message-ID: <20250
.)
riscv_exception 2 (illegal_instruction) on epc 0x1053a
Illegal instruction (core dumped)
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20250106173734.412353-3-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
target/riscv/op_helper.c
ys present)
- Shgatpa (always present)
We can claim support for 'sha' by checking if we have RVH and ssstateen.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20241218114026.1652352-10-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
-
The following changes since commit 0e3aff9ec34059512d597eacfcf4d1b5d4570c50:
Merge tag 'pull-10.0-gdb-plugins-doc-updates-170125-1' of
https://gitlab.com/stsquad/qemu into staging (2025-01-17 10:13:07 -0500)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags
u-Daudé
Reviewed-by: Alistair Francis
Message-ID: <20250112231344.34632-2-phi...@linaro.org>
Signed-off-by: Alistair Francis
---
target/riscv/kvm/kvm_riscv.h | 4 +++-
hw/riscv/virt.c | 2 +-
target/riscv/kvm/kvm-cpu.c | 4 ++--
3 files changed, 6 insertions(+), 4 deletio
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20250106102346.1100149-3-baturo.ale...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 8
target/riscv/cpu_bits.
x27;s disable Smrnmi for the 'max' type CPU for
now. We can re-enable it once OpenSBI includes proper support for it.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Fran
From: Daniel Henrique Barboza
shcounterenw is defined in RVA22 as:
"For any hpmcounter that is not read-only zero, the corresponding bit in
hcounteren must be writable."
This is always true in TCG so let's claim support for it.
Signed-off-by: Daniel Henrique Barboza
Review
ue for TCG.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20241218114026.1652352-9-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c| 1 +
tests/data/acpi/riscv64/virt/RHCT | Bin 382 -> 390 bytes
2 files c
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: LIU Zhiwei
Message-ID: <20250106102346.1100149-5-baturo.ale...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 3 +++
target
We already have sstvala, and our vstval follows the same rules as stval,
so we can claim to support shvstvala too.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20241218114026.1652352-5-dbarb...@ventanamicro.com>
Signed-off-by: Alist
for it.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20241218114026.1652352-7-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c| 1 +
tests/data/acpi/riscv64/virt/RHCT | Bin 364 -> 374 bytes
2 fi
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-ID: <20250106102346.1100149-6-baturo.ale...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/translate.c | 22 --
target
ff-by: Yanfeng Liu
Reviewed-by: Alistair Francis
Message-ID:
Signed-off-by: Alistair Francis
---
target/riscv/gdbstub.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index c07df972f1..18e88f416a 100644
From: Craig Blackmore
Replace `continus` with `continuous`.
Signed-off-by: Craig Blackmore
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Max Chou
Reviewed-by: Richard Henderson
Message-ID: <20241218142353.1027938-2-craig.blackm...@embecosm.com>
Signed-off-by: Alistair F
g a double trap. OpenSBI does not currently support it so disable
> it for the max cpu to avoid breaking regression tests.
>
> Signed-off-by: Clément Léger
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> Note: this is a resend of patch 9/9 from the double trap series which
From: Kaiwen Xue
Since xiselect and xireg also will be of use in sxcsrind, AIA should
have its own separated interface when those CSRs are accessed.
Signed-off-by: Kaiwen Xue
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-ID: <20250110-counter_delegation-v5-2-e83d79
We already have sstvala, and our vstval follows the same rules as stval,
so we can claim to support shvstvala too.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20241218114026.1652352-5-dbarb...@ventanamicro.com>
Signed-off-by: Alist
1 - 100 of 2122 matches
Mail list logo
