On Thu, Jan 16, 2025 at 12:18 AM Jason Chien <jason.ch...@sifive.com> wrote:
>
> The header contains duplicate macro definitions.
> This commit eliminates the duplicate part.
>
> Signed-off-by: Jason Chien <jason.ch...@sifive.com>
> Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> hw/riscv/riscv-iommu-bits.h | 22 ++++++----------------
> 1 file changed, 6 insertions(+), 16 deletions(-)
>
> diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h
> index 485f36b9c9..de599b80d6 100644
> --- a/hw/riscv/riscv-iommu-bits.h
> +++ b/hw/riscv/riscv-iommu-bits.h
> @@ -50,8 +50,14 @@ struct riscv_iommu_pq_record {
> #define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33)
> #define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34)
> #define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40)
> +
> /* Payload fields */
> +#define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0)
> +#define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1)
> +#define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2)
> #define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0)
> +#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3)
> +#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12)
>
> /* Common field positions */
> #define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10)
> @@ -382,22 +388,6 @@ enum riscv_iommu_fq_ttypes {
> RISCV_IOMMU_FW_TTYPE_PCIE_MSG_REQ = 9,
> };
>
> -/* Header fields */
> -#define RISCV_IOMMU_PREQ_HDR_PID GENMASK_ULL(31, 12)
> -#define RISCV_IOMMU_PREQ_HDR_PV BIT_ULL(32)
> -#define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33)
> -#define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34)
> -#define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40)
> -
> -/* Payload fields */
> -#define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0)
> -#define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1)
> -#define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2)
> -#define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0)
> -#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3)
> -#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12)
> -
> -
> /*
> * struct riscv_iommu_msi_pte - MSI Page Table Entry
> */
> --
> 2.43.2
>
>
