On 5/5/25 19:02, Tomita Moeko wrote:
As proposed in a previous discussion [1], detect IGD devices based on
whether it has VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION exposed by kernel
and enables OpRegion access by default. This enables out-of-the-box
display output support for IGD passthrough without
On Mon, 2025-05-05 at 08:55 +0200, Shalini Chellathurai Saroja wrote:
> On 2025-04-28 11:22, Janis Schoetterl-Glausch wrote:
> > On Thu, 2025-04-10 at 17:09 +0200, Shalini Chellathurai Saroja wrote:
> > > Implement the Service-Call Logical Processor (SCLP) event
> > > type Control-Program Identific
On Mon, 2025-05-05 at 10:54 +0200, Shalini Chellathurai Saroja wrote:
> On 2025-04-28 14:05, Nina Schoetterl-Glausch wrote:
> > On Thu, 2025-04-10 at 17:09 +0200, Shalini Chellathurai Saroja wrote:
> > > Add Control-Program Identification (CPI) device to QOM only when the
> > > virtual
> > > machi
On Mon, May 05, 2025 at 06:38:17PM +0200, Eric Auger wrote:
> > +/**
> > + * struct HostIOMMUDeviceIOMMUFDCaps - Define host IOMMU device
> > capabilities.
> > + *
> > + * @type: host platform IOMMU type.
> > + *
> > + * @hw_caps: host platform IOMMU capabilities (e.g. on IOMMUFD this
> > represe
From: Thomas Huth
The s390-ccw-virtio-2.10 machine is older than 6 years, so according
to our machine support policy, it can be removed now.
Signed-off-by: Thomas Huth
---
hw/s390x/s390-virtio-ccw.c | 12
1 file changed, 12 deletions(-)
diff --git a/hw/s390x/s390-virtio-ccw.c b/h
From: Thomas Huth
The s390-ccw-virtio-3.1 machine is older than 6 years, so according to
our machine support policy, it can be removed now. The v3.1 CPU feature
group gets merged into the minimum CPU feature group now.
Signed-off-by: Thomas Huth
---
hw/s390x/s390-virtio-ccw.c | 16 ---
The machine types up to s390-ccw-virtio-4.0 are older than 6 years
and thus, according to our support policy, are scheduled for being
deletion now. These patches remove the machines and clean up the
related compatibility handling that is not required anymore.
v2:
- Some patches are already upstrea
From: Thomas Huth
The s390-ccw-virtio-2.11 machine is older than 6 years, so according
to our machine support policy, it can be removed now.
Signed-off-by: Thomas Huth
---
hw/s390x/s390-virtio-ccw.c | 25 -
1 file changed, 25 deletions(-)
diff --git a/hw/s390x/s390-vir
From: Thomas Huth
The s390-ccw-virtio-3.0 machine is older than 6 years, so according to
our machine support policy, it can be removed now.
Signed-off-by: Thomas Huth
---
hw/s390x/s390-virtio-ccw.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/hw/s390x/s390-virtio-ccw.c b
From: Thomas Huth
The s390-ccw-virtio-4.0 machine is older than 6 years, so according to
our machine support policy, it can be removed now. The corresponding
v4.0 CPU feature group gets merged into the minimum feature group now.
Signed-off-by: Thomas Huth
---
hw/s390x/s390-virtio-ccw.c | 14 -
From: Thomas Huth
Now that the machine types 2.11 and older have been removed, we
don't need the "allow_all_mask_sizes" compatibility handling code
anymore and can remove it now.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
hw/s390x/event-facility.c | 37 +---
From: Thomas Huth
The s390-ccw-virtio-2.12 machine is older than 6 years, so according to
our machine support policy, it can be removed now.
Signed-off-by: Thomas Huth
---
hw/s390x/s390-virtio-ccw.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/hw/s390x/s390-virtio-ccw.c b
From: Thomas Huth
The s390-ccw-virtio-3.0 machine was the last one that used the
hpage_1m_allowed switch. Since we removed this machine type, we
can now remove the switch and the related code, too. This allows
us to get rid of the get_machine_class() hack and the big fat
warning comment there.
R
From: Thomas Huth
Now that the v2.11 machine type has been removed, it does not make
sense to keep the qemu_V2_11 feature set around. This is rather
the (minimum) feature set of the oldest supported machine now, so
rename it to qemu_MIN.
Signed-off-by: Thomas Huth
---
target/s390x/gen-features
Hi Cédric
> Subject: Re: [PATCH v1 09/22] hw/misc/aspeed_hace: Ensure HASH_IRQ is
> always set to prevent firmware hang
>
> On 3/21/25 10:26, Jamin Lin wrote:
> > Currently, if the program encounters an unsupported algorithm, it does
> > not set the HASH_IRQ bit in the status register and send an
> You need to explain in greater details
> what you are trying to solve.
As I mentioned earlier, let's say you don't initialize the vertical display
end registers, and set the minimum scanline register, the emulation will
then have to allocate some display buffer, but because the vertical display
Cc'ing Paolo
On 30/04/2025 2:48 pm, CLEMENT MATHIEU--DRIF wrote:
> This series introduces 2 fixes and improves locking style
> consistency in the VT-d device.
>
> Changes since v4:
> - Re-check if the address space is present once both bql and
> iommu lock are held.
>
>
> Clement
lrdr-capacity contains phys field which communicates the maximum address
in bytes and therefore, the most memory that can be allocated to this
partition. This is usually populated when maxmem is provided alongwith
memory size on qemu command line. However since maxmem is an optional
param, this lea
> This won't work on read-only storage.
>
> > +}
> > }
> > qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal);
> >
> > @@ -194,7 +206,8 @@ static void npcm845_evb_init(MachineState *machine)
> > qdev_realize(DEVICE(soc), NULL, &error_fatal);
> >
> > npcm8xx_l
Il mar 6 mag 2025, 01:06 John Snow ha scritto:
>
>
> On Mon, May 5, 2025 at 11:36 AM Paolo Bonzini wrote:
>
>> On 5/5/25 14:19, Akihiko Odaki wrote:
>> > Supersedes: <20250120-sphinx-v1-0-65151b444...@daynix.com>
>> > ("[PATCH 0/2] docs: Bump sphinx to 8.1.3")
>>
>> Sphinx 8 requires Python 3.11
> This fails on top of current master, please take a look:
>
> $ QTEST_LOG=1 QTEST_QEMU_BINARY=./qemu-system-aarch64
> ./tests/qtest/npcm8xx_pspi-test
> # random seed: R02S03f79fc48ba73b76c881f93f90b015e9
> 1..3
> # Start of aarch64 tests
> # Start of npcm8xx_pspi tests
> # starting QEMU: exec ./q
Replace legacy reset callback register device_class_set_legacy_reset()
with new function resettable_class_set_parent_phases(). With new API,
it will call reset callback of parent object.
The internal state has been cleared in parent object
LOONGARCH_PIC_COMMON, here parent_phases.hold() is directl
XSDT table is introduced in ACPI Specification 5.0, it supports 64-bit
address in the table. There is LoongArch system support from ACPI
Specification 6.4 and later, XSDT is supported by LoongArch system.
Here replace RSDT with XSDT table.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/l
Add reset support with ipi object, register reset callback and clear
internal registers when virt machine resets.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_ipi.c | 29 +
include/hw/intc/loongarch_ipi.h | 1 +
2 files changed, 30 ins
Add reset support with extioi irqchip, and register reset callback
support with new API resettable_class_set_parent_phases(). Clear
internal HW registers and SW state when virt machine resets.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_extioi_common.c | 41 +
Add reset support with LoongArch pci irqchip, and register reset
callback support with new API resettable_class_set_parent_phases().
Clear internal HW registers and SW state when virt machine resets.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pic_common.c | 25 +
With load_elf() api, image load low address and high address is converted
to physical address if parameter translate_fn is provided. However
executing entry address is still virtual address. Here convert entry
address into physical address, since MMU is disabled when system power on,
the first PC i
The following changes since commit 5134cf9b5d3aee4475fe7e1c1c11b093731073cf:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2025-04-30 13:34:44 -0400)
are available in the Git repository at:
https://github.com/bibo-mao/qemu.git tags/pull-loongarch-20250506
Replace legacy reset callback register device_class_set_legacy_reset()
with new function resettable_class_set_parent_phases(). With new API,
it will call reset callback of parent object and then itself.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_extioi.c | 12 ++
On LoongArch virt machine, the default OEM ID and OEM table ID is
"BOCHS " and "BXPC". Here property x-oem-id and x-oem-table-id
is added on virt machine to set customized OEM ID and OEM table ID.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/loongarch/virt.c | 58 +++
Hi Eric,
On 5/5/25 11:19, Eric Auger wrote:
Hi Gustavo,
On 5/5/25 2:29 PM, Gustavo Romero wrote:
Hi Eric,
On 5/5/25 04:13, Eric Auger wrote:
On 5/4/25 11:56 PM, Gustavo Romero wrote:
Fix typo in QEMU's ACPI PCI hotplug API function name that checks
whether a given bus is hotplug-capable.
I'm also ignorant of plugins, but (a) if not enabling plugins is a nop
and (b) plugins either work or fail completely, then I think we can
enable them. If they cause problems when not enabled by the user,
though, we'll likely have to revert.
I don't know enough about them, though, to review.
Warn
Hi Eric,
On 4/28/25 07:25, Eric Auger wrote:
Propagate the type of pci hotplug mode downto the gpex
acpi code. In case machine acpi_pcihp is unset we configure
pci native hotplug on pci0. For expander bridges we keep
legacy pci native hotplug, as done on x86 q35.
Signed-off-by: Eric Auger
---
Hi Eric,
On 4/28/25 07:25, Eric Auger wrote:
acpi_dsdt_add_pci_osc() name is confusing as it gives the impression
it appends the _OSC method but in fact it also appends the _DSM method
for the host bridge. Let's split the function into two separate ones
and let them return the method Aml pointer
Hi Eric,
On 4/28/25 07:25, Eric Auger wrote:
Add a new argument to acpi_dsdt_add_pci_osc to be able to disable
native pci hotplug.
Signed-off-by: Eric Auger
---
hw/pci-host/gpex-acpi.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/
Hi Eric,
On 4/28/25 07:25, Eric Auger wrote:
We plan to reuse build_x86_acpi_pci_hotplug() implementation
for ARM so let's move the code to generic pcihp.
Associated static aml_pci_pdsm() helper is also moved along.
build_x86_acpi_pci_hotplug is renamed into build_acpi_pci_hotplug().
No code c
Hi Eric,
On 4/28/25 07:25, Eric Auger wrote:
acpi_pcihp VirtMachineClass state flag will allow
to opt in for acpi pci hotplug. This is guarded by a
class no_acpi_pcihp flag to manage compats (<= 10.0
machine types will not support ACPI PCI hotplug).
Machine state acpi_pcihp flag msu be set befo
Hi Eric,
On 4/28/25 07:25, Eric Auger wrote:
Rename build_append_notfication_callback into
build_append_notification_callback
Signed-off-by: Eric Auger
---
hw/i386/acpi-build.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-bu
Hi Eric,
On 4/28/25 07:25, Eric Auger wrote:
Signed-off-by: Eric Auger
---
hw/acpi/generic_event_device.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
index c85d97ca37..7b2d582fff 100644
--- a/h
Hi Eric,
On 4/28/25 07:25, Eric Auger wrote:
Signed-off-by: Eric Auger
---
hw/pci/pcie_port.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/pci/pcie_port.c b/hw/pci/pcie_port.c
index c73db30e98..072500ed34 100644
--- a/hw/pci/pcie_port.c
+++ b/hw/pci/pcie_port.c
aarch64 specific code is guarded by cpu_isar_feature(aa64*), so it's
safe to expose it.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/tcg/tlb-insns.c | 7 ---
target/arm/tcg/meson.build | 2 +-
2 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/tar
Allows to include target/arm/tcg/tlb-insns.c only for system targets.
Signed-off-by: Pierrick Bouvier
---
target/arm/helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ef9594eec29..6eaf6b3a04e 100644
--- a/target/arm/helper.c
+++ b/targ
On MacOS x86_64:
In file included from ../target/i386/hvf/x86_task.c:13:
/Users/runner/work/qemu/qemu/include/system/hvf.h:42:5: error: unknown type
name 'vaddr'
vaddr pc;
^
/Users/runner/work/qemu/qemu/include/system/hvf.h:43:5: error: unknown type
name 'vaddr'
vaddr saved_insn;
Patches left for review:
- [PATCH v6 04/50] meson: apply target config for picking files from
libsystem and libuser
- [PATCH v6 41/50] target/arm/tcg/vec_internal: use forward declaration
for CPUARMState
- [PATCH v6 42/50] target/arm/tcg/crypto_helper: compile file once
- [PATCH v6 47/50] targ
Signed-off-by: Pierrick Bouvier
---
target/arm/tcg/crypto_helper.c | 6 --
target/arm/tcg/meson.build | 5 -
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c
index 7cadd61e124..3428bd1bf0b 100644
--- a/targe
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/meson.build | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 29a36fb3c5e..bb1c09676d5 100644
--- a/target/
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/tcg/tlb_helper.c | 3 ++-
target/arm/tcg/meson.build | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
index 4e3e96a2af0..feaa6025fc6 100
Signed-off-by: Pierrick Bouvier
---
target/arm/tcg/vfp_helper.c | 4 +++-
target/arm/tcg/meson.build | 3 ++-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/vfp_helper.c b/target/arm/tcg/vfp_helper.c
index b32e2f4e27c..b1324c5c0a6 100644
--- a/target/arm/tcg/vfp_he
Allow later commits to include only the "new" tcg/helper.h, thus
preventing to pull aarch64 helpers (+ target/arm/helper.h contains a
ifdef TARGET_AARCH64).
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/helper.h | 1152 +-
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 95a2b077dd6..7db573f4a97 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.
Needed so this header can be included without requiring cpu.h.
Signed-off-by: Pierrick Bouvier
---
target/arm/tcg/vec_internal.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h
index 6b93b5aeb94..c02f9c37f83 100644
--- a/target/
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/meson.build | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 48a6bf59353..c8c80c3f969 100644
--- a/target/arm/meson.build
+++ b/target/arm/meso
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/tcg/neon_helper.c | 4 +++-
target/arm/tcg/meson.build | 3 ++-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c
index e2cc7cf4ee6..2cc8241f1e
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/meson.build | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index c8c80c3f969..06d479570e2 100644
--- a/target/arm/meson.build
+++ b/target/arm/meso
Other accelerators define a CONFIG_{accel}_IS_POSSIBLE when
COMPILING_PER_TARGET is not defined, except hvf.
Without this change, target/arm/cpu.c can't find hvf_enabled.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/system/hvf.h | 14 +-
accel/hvf/hvf
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 06d479570e2..95a2b077dd6 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7fb6e886306..10384132090 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/helper.h| 2 +-
target/arm/tcg/op_helper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 95b9211c6f4..0a4fc90fa8b 100644
--- a/target/arm
Add a forward decl for struct kvm_vcpu_init to avoid pulling all kvm
headers.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/kvm_arm.h | 83 +--
target/arm/kvm-stub.c | 77 +++
2 files ch
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 6e0327b6f5b..151184da71c 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.
associated define_arm_cp_regs are guarded by
"cpu_isar_feature(aa64_*)", so it's safe to expose that code for arm
target (32 bit).
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Pierrick Bouvier
---
target/arm/helper.c | 7 ---
1 file changed, 7 deletions
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/tcg/iwmmxt_helper.c | 4 +++-
target/arm/tcg/meson.build | 3 ++-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/iwmmxt_helper.c b/target/arm/tcg/iwmmxt_helper.c
index 610b1b2103e..ba
Associated code is protected by cpu_isar_feature(aa64*)
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Pierrick Bouvier
---
target/arm/arch_dump.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
index c
They were hiding aarch64_sve_narrow_vq and aarch64_sve_change_el, which
we can expose safely.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/helper.c | 8
1 file changed, 8 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7e07ed0
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/tcg/hflags.c| 4 +++-
target/arm/tcg/meson.build | 8 +++-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
index e51d9f7b159..9fdc18d5ccb 100644
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/tcg/arith_helper.c | 5 +++--
target/arm/tcg/meson.build| 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/arith_helper.c b/target/arm/tcg/arith_helper.c
index 9a555c7966c..670139
Those become needed once kvm_enabled can't be known at compile time.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/kvm-stub.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c
index 4806365cdc5..34e57fab
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Pierrick Bouvier
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 10384132090..7daf44e199d 100644
--- a/target/arm/helper.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 7db573f4a97..6e0327b6f5b 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.
This exposes two new subsections for arm: vmstate_sve and vmstate_za.
Those sections have a ".needed" callback, which already allow to skip
them when not needed.
vmstate_sve .needed is checking cpu_isar_feature(aa64_sve, cpu).
vmstate_za .needed is checking ZA flag in cpu->env.svcr.
Reviewed-by:
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Pierrick Bouvier
---
target/arm/debug_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 357bc2141ae..50ef5618f51 100644
--- a/
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index bb1c09676d5..b404fa54863 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/meson.build | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index c39ddc4427b..89e305eb56a 100644
--- a/target/arm/meson.build
+++ b/target/arm
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/helper.h| 2 +-
target/arm/tcg/tlb_helper.c| 2 +-
target/arm/tcg/translate-a64.c | 2 +-
target/arm/tcg/translate.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm
Allow to get rid of CONFIG_KVM in target/arm/cpu.c
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Pierrick Bouvier
---
target/arm/kvm_arm.h | 2 ++
target/arm/cpu.c | 31 ---
target/arm/kvm-stub.c | 5 +
target/arm/kvm.
Needed in target/arm/cpu.c once kvm is possible.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/kvm-stub.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c
index 2b73d0598c1..e34d3f5e6b4 100644
--- a/target/arm
Defined as an alias of i32/i64 depending on host pointer size.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/tcg/tcg-op-common.h| 1 +
include/tcg/tcg.h | 14 ++
include/exec/helper-head.h.inc | 11 +++
tcg/tcg.c
Avoid pulling helper.h which contains TARGET_AARCH64.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/debug_helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 473ee2af38e..357b
semihosting code needs to be included only if CONFIG_SEMIHOSTING is set.
However, this is a target configuration, so we need to apply it to the
libsystem libuser source sets.
Acked-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
meson.build | 26 ++
1 file chan
Call is guarded by is_a64(env), so it's safe to expose without needing
to assert anything.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 37b11e8866f..0
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/machine.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 978249fb71b..f7956898fa1 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@
This function needs 64 bit compare exchange, so we hide implementation
for hosts not supporting it (some 32 bit target, which don't run 64 bit
guests anyway).
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/ptw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/meson.build | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 151184da71c..29a36fb3c5e 100644
--- a/target/arm/meson.build
+++ b/target/arm/m
More work toward single-binary.
Some files have external dependencies for the single-binary:
- target/arm/gdbstub.c: gdbhelpers
- target/arm/arm-qmp-cmds.c: qapi
- target/arm/tcg/translate*: need deep cleanup in include/tcg
- target/arm/tcg/cpu*: need TargetInfo implemented for arm/aarch64
- targe
It could be squashed with commit introducing it, but I would prefer to
introduce target/arm/cpu.c first.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/meson.build | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/arm/meson.
Need to stub cpu64 finalize functions.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.c | 2 --
target/arm/cpu32-stubs.c | 26 ++
target/arm/meson.build | 11 +++
3 files changed,
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/meson.build | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index de214fe5d56..48a6bf59353 100644
--- a/target/arm/meson.build
+++ b/target
From: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Pierrick Bouvier
---
target/arm/internals.h | 6 +++---
target/arm/hyp_gdbstub.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git
sextract64 returns a signed value.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Pierrick Bouvier
---
target/arm/ptw.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index e0e82ae507f..26c52e6b03e
Reviewed-by: Richard Henderson
Reviewed-by: Anton Johansson
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 07f279fec8c..37b11e8866f 100644
--- a/target/arm/cpu.c
+++ b/target/ar
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/kvm_arm.h | 4 +++-
target/arm/kvm.c | 13 -
target/arm/machine.c | 8 +---
3 files changed, 16 insertions(+), 9 deletions(-)
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index d156c7
Following what we did for hw/, we need target specific common libraries
for target. We need 2 different libraries:
- code common to a base architecture
- system code common to a base architecture
For user code, it can stay compiled per target for now.
Reviewed-by: Richard Henderson
Signed-off-by
On Mon, May 5, 2025 at 11:36 AM Paolo Bonzini wrote:
> On 5/5/25 14:19, Akihiko Odaki wrote:
> > Supersedes: <20250120-sphinx-v1-0-65151b444...@daynix.com>
> > ("[PATCH 0/2] docs: Bump sphinx to 8.1.3")
>
> Sphinx 8 requires Python 3.11 on the other hand; not an objection, just
> a reminder for m
On Wed, Apr 30, 2025 at 6:45 AM Markus Armbruster wrote:
> Thomas Huth writes:
>
> > Hi!
> >
> > On 25/04/2025 17.13, Markus Armbruster wrote:
> >> Philippe Mathieu-Daudé writes:
> >>> On 25/4/25 14:07, Thomas Huth wrote:
> From: Thomas Huth
> Python 3.8 went "end of life" in Octobe
Hi Alistair,
I think we should push this upstream and see what happens. We'll have a
full release cycle to undo the change in case we find unintended side
effects. I'm fairly optimistic that this change will be a no-op for most
users and will benefit us when we'll have to deal with RVA23 specifi
address_space_write_rom_internal can take in a NULL pointer for ptr if
it's only doing cache flushes instead of populating the ROM.
However, if building with --enable-ubsan, incrementing buf causes ubsan
to go off when doing cache flushes, since it will trigger on pointer
arithmetic on a NULL poin
Peter Xu writes:
> On Wed, Apr 16, 2025 at 10:43:55AM -0300, Fabiano Rosas wrote:
>> When qatomic_fetch_inc() started being used to count the number of
>> packets sent, the printing of the number of packets received stopped
>> matching the number of packets sent.
>>
>> Fix by moving the incremen
On 5/5/25 15:26, John Levon wrote:
On Mon, May 05, 2025 at 02:06:03PM +0200, Cédric Le Goater wrote:
!---|
CAUTION: External Email
|---!
On 4/30/25 21:39, John Lev
On Wed, Apr 16, 2025 at 10:43:55AM -0300, Fabiano Rosas wrote:
> When qatomic_fetch_inc() started being used to count the number of
> packets sent, the printing of the number of packets received stopped
> matching the number of packets sent.
>
> Fix by moving the increment of the number of packets
On 5/5/25 19:02, Tomita Moeko wrote:
As proposed in a previous discussion [1], detect IGD devices based on
whether it has VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION exposed by kernel
and enables OpRegion access by default. This enables out-of-the-box
display output support for IGD passthrough without
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