Bibo Mao writes:
> There is NULL pointer checking function error_propagate() already,
> it is not necessary to add checking for function parameter. Here remove
> NULL pointer checking with function parameter.
I believe the title "Remove unnecessary NULL pointer" and this paragraph
are remnants o
Booting the microchip-icicle-kit machine using the latest PolarFire SoC
Hart Software Services (HSS) no longer works since Qemu lacks support
for several registers (clocks, DRAM controller). Also reading from the
SDCard does not work currently.
In order to allow tests runs for real-time kernels su
LGTM, thanks!
Reviewed-by: zhenwei pi
On 3/12/25 18:11, Markus Armbruster wrote:
When cryptodev_lkcf_set_op_desc() fails, we report an error, but
continue anyway. This is wrong. We then pass a non-null @local_error
to various functions, which could easily fail error_setv()'s assertion
on fai
Bibo Mao writes:
> In function virt_cpu_irq_init(), there is notification with ipi and extioi
> interrupt controller for cpu creation. Local variable with error type is
> used, however there is no check with its return value.
Good catch.
When the first call fails, we pass non-null @err to the s
Signed-off-by: Sebastian Huber
---
hw/misc/mchp_pfsoc_sysreg.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c
index 7876fe0c5b..08196525aa 100644
--- a/hw/misc/mchp_pfsoc_sysreg.c
+++ b/hw/misc/mchp_pfsoc_sysreg.c
@@ -27,7 +27,
Mention that running the HSS no longer works. Document the changed boot
options. Reorder documentation blocks. Update URLs.
Signed-off-by: Sebastian Huber
---
docs/system/riscv/microchip-icicle-kit.rst | 124 +++--
1 file changed, 43 insertions(+), 81 deletions(-)
diff --git
Further customize the -bios and -kernel options behaviour for the
microchip-icicle-kit machine. If "-bios none -kernel filename" is
specified, then do not load a firmware and instead only load and start
the kernel image.
For test runs, use an approach similar to
riscv_find_and_load_firmware().
S
If the kernel entry is in the high DRAM area, place the FDT into this
area.
Signed-off-by: Sebastian Huber
Reviewed-by: Alistair Francis
---
hw/riscv/microchip_pfsoc.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip
This property enables the setting of the CLINT timebase frequency
through the command line, for example:
-machine microchip-icicle-kit,clint-timebase-frequency=1000
Signed-off-by: Sebastian Huber
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/microchip_pfsoc.c | 49
Alejandro,
On 3/11/2025 8:54 PM, Alejandro Jimenez wrote:
> The AMD I/O Virtualization Technology (IOMMU) Specification (see Table 8: V,
> TV, and GV Fields in Device Table Entry), specifies that a DTE with V=0,
> TV=1 does not contain a valid address translation information. If a request
> requ
> -Original Message-
> From: Nicolin Chen
> Sent: Monday, March 17, 2025 8:19 PM
> To: Jason Gunthorpe
> Cc: Eric Auger ; Shameerali Kolothum Thodi
> ; qemu-...@nongnu.org;
> qemu-devel@nongnu.org; peter.mayd...@linaro.org; ddut...@redhat.com;
> berra...@redhat.com; nath...@nvidia.com;
Array type vmstate has the VMStateField with `num` equals its length.
When the varray vmstate is built based a array type, the `num` field
should be cleaned to 0, because varray uses `num_offset` instead of
`num` to store elements number information.
Signed-off-by: Zhao Liu
---
rust/qemu-api/sr
On 3/18/25 11:18, Andreas Schwab wrote:
Is there a generic way for a program to detect that is it being run
inside the linux-user emulation?
Yes, having a reliable way to detect it would be good.
My current (unreliable) way to detect it is using uname.
The kernel string and arch name don't mat
On Tue, 18 Mar 2025 at 13:55, Daniel P. Berrangé wrote:
>
> On Tue, Mar 18, 2025 at 01:06:17PM +, Peter Maydell wrote:
> > The difficulty with vfork() (and, more generally, with various of
> > the clone() syscall flag combinations) is that because we use the
> > host libc we are restricted to
On 3/18/25 17:30, Pierrick Bouvier wrote:
include/exec/watchpoint.h | 41 +
include/hw/core/cpu.h | 30 -
accel/tcg/tcg-accel-ops.c | 1 +
system/watchpoint.c | 1 +
target/arm/debug_helper.c
On Tue, Mar 18, 2025 at 09:31:35PM -0300, Jason Gunthorpe wrote:
> On Tue, Mar 18, 2025 at 07:31:36PM +0100, Eric Auger wrote:
> > Nevertheless I don't think anything prevents the acceleration granted
> > device from also working with virtio/vhost devices for instance unless
> > you unplug the exis
zhenwei pi writes:
> On 3/18/25 21:21, Markus Armbruster wrote:
>> zhenwei pi writes:
>>
>>> Hi Markus,
>>>
>>> Current code style seems buggy, I think the main reason is that the Error
>>> *errp is not generated at right place. keyctl_pkey_XXX fails without new
>>> error, qcrypto_akcipher_XX
Il mar 18 mar 2025, 07:16 Zhao Liu ha scritto:
> > Would it be possible, or make sense, to move most of the code for
> > field_exists inside .with_exist_check()?
> >
>
> If so, the method would be like:
>
> pub fn with_exist_check(
> mut self,
> _cb: F
> ) -> Self
>
On Wed, Mar 19, 2025 at 12:22 PM Huang Borong wrote:
>
> This implementation provides emulation for the Xiangshan Kunminghu SoC,
> including support for UART, CLINT, IMSIC, and APLIC devices.
> More details can be found at
> https://github.com/OpenXiangShan/XiangShan
Can you add an entry to `docs
Our KVM code includes backwards compatibility support for ancient
kernels which don't support the KVM_ARM_PREFERRED_TARGET ioctl. This
ioctl was introduced in kernel commit 42c4e0c77ac91 in September
2013 and is in v3.12, so it's reasonable to assume it's present.
(We already dropped support for
The vmstate has too many combinations of VMStateFlags and VMStateField.
Currently, the best way to test is to ensure that the Rust vmstate
definition is consistent with the (possibly corresponding) C version.
Add a unit test to cover some patterns accepted by vmstate_of macro,
which correspond to
On Fri, 14 Mar 2025 at 18:32, Bernhard Beschow wrote:
>
> The SoC has three SPI controllers, not four. Remove the extra define of an SPI
> IRQ.
>
> Fixes: 06908a84f036 "hw/arm/fsl-imx8mp: Add SPI controllers"
> Signed-off-by: Bernhard Beschow
Reviewed-by: Peter Maydell
thanks
-- PMM
Hi,
This is my v3, based on aa90f1161bb17 ("Merge tag 'migration-20250314-pull
-request' of https://gitlab.com/farosas/qemu into staging") at master
branch.
Compared with v2:
* the patch 10 drops `with_exist_check()` and `with_validate_flag()`.
* patch 15 is newly added to clen up VMStateFlags
zhenwei pi writes:
> Hi Markus,
>
> Current code style seems buggy, I think the main reason is that the Error
> *errp is not generated at right place. keyctl_pkey_XXX fails without new
> error, qcrypto_akcipher_XXX fails with new error, but they are in the same
> switch-case code block. If we
On Thu, Mar 13, 2025 at 4:27 PM ~yuming wrote:
>
> From: Yu-Ming Chang
>
> For privilege version 1.12 or newer, C always implies Zca. We can only
> check ext_zca to allow 16-bit aligned PC addresses. For older privilege
> versions, we only check C.
>
> Signed-off-by: Yu-Ming Chang
Thanks!
Appl
On 18/3/25 18:50, Peter Maydell wrote:
On Tue, 18 Mar 2025 at 17:42, Philippe Mathieu-Daudé wrote:
On 18/3/25 05:51, Pierrick Bouvier wrote:
Directly condition associated calls in target/arm/helper.c for now.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h| 8
target/
On Tue, 18 Mar 2025 at 06:14, Thomas Huth wrote:
>
> From: Thomas Huth
>
> We don't use the term "integration tests" for these kind of tests
> anymore, it's "functional tests" nowadays.
>
> Suggested-by: Niek Linnenbank
> Signed-off-by: Thomas Huth
> ---
> docs/system/arm/bananapi_m2u.rst | 6
The vmstate has too many combinations of VMStateFlags and VMStateField.
Currently, the best way to test is to ensure that the Rust vmstate
definition is consistent with the (possibly corresponding) C version.
Add a unit test to cover some patterns accepted by vmstate_of macro,
which correspond to
Gather all VFIOcontainer related declarations into "container.h" to
reduce exposure of VFIO internals in "hw/vfio/vfio-common.h".
These declarations are made available externally for PPC and s390x.
Signed-off-by: Cédric Le Goater
---
include/hw/vfio/vfio-common.h| 19 -
incl
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:29 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
The VMState type bound is not used in with_varray_flag().
And for vmstate_struct, Rust cannot infer the type of `num` from the
call_func_with_field(), so this causes the compiling error because it
complains "cannot satisfy `_: VMState`" in with_varray_flag().
Note Rust can infer the type in vmsta
From: Denis Rastyogin
This error was discovered by fuzzing qemu-img.
The qcow2_refresh_limits() is missing a check
for the s->crypto pointer, which can lead to
a null pointer dereference. This commit adds the necessary check.
Reported-by: Leonid Reviakin
Signed-off-by: Denis Rastyogin
---
bl
Remove the `unsafe` block of vmsd, because vmsd (passed to
vmstate_struct) is defined in Rust side now, and it doesn't need
`unsafe`.
Signed-off-by: Zhao Liu
---
rust/qemu-api/src/vmstate.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/rust/qemu-api/src/vmstate.rs b/rust/q
"hw/vfio/vfio-common.h" has been emptied of most of its declarations
by the previous changes and the only declarations left are related to
VFIODevice. Rename it to "hw/vfio/vfio-device.h" and make the
necessary adjustments.
Signed-off-by: Cédric Le Goater
---
hw/vfio/migration-multifd.h
The varry of structure created by vmstate_struct is different with
vmstate_of. This is because vmstate_struct uses the `vmsd` to traverse
the vmstates of structure's fields, rather than treating the structure
directly as a well-defined vmstate.
Therefore, there's no need to check array flag when b
TYPE_FSL_IMX8MP is created using object_new(), so must be realized with
qdev_realize_and_unref() to keep the reference counting intact.
Signed-off-by: Bernhard Beschow
---
hw/arm/imx8mp-evk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-
There is NULL pointer checking function error_propagate() already,
it is not necessary to add checking for function parameter. Here remove
NULL pointer checking with function parameter.
Since function will return directly when there is error report, this
patch removes combination about error_setg(
On 3/17/25 21:51, Pierrick Bouvier wrote:
Including "cpu.h" from code that is not compiled per target is ambiguous
by definition. Thus we introduce a conditional include, to allow every
architecture to set this, to point to the correct definition.
hw/X or target/X will now include directly "targ
在 2025/3/7 下午3:13, Bibo Mao 写道:
Replace legacy reset callback register device_class_set_legacy_reset()
with new function resettable_class_set_parent_phases(). With new API,
it will call reset callback of parent object and then itself.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi.c
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 10 --
1 file changed, 10 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
在 2025/3/7 下午3:13, Bibo Mao 写道:
Add reset support with LoongArch pci irqchip, and register reset
callback support with new API resettable_class_set_parent_phases().
Clear internal HW registers and SW state when virt machine resets.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pic_common.c
在 2025/3/7 下午3:13, Bibo Mao 写道:
Add reset support with ipi object, register reset callback and clear
internal registers when virt machine resets.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 29 +
include/hw/intc/loongarch_ipi.h | 1 +
2 files c
在 2025/3/7 下午3:13, Bibo Mao 写道:
Add reset support with extioi irqchip, and register reset callback
support with new API resettable_class_set_parent_phases(). Clear
internal HW registers and SW state when virt machine resets.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi_common.c
在 2025/3/7 下午3:13, Bibo Mao 写道:
Replace legacy reset callback register device_class_set_legacy_reset()
with new function resettable_class_set_parent_phases(). With new API,
it will call reset callback of parent object.
The internal state has been cleared in parent object
LOONGARCH_PIC_COMMON, he
When pass a varray to vmstate_struct, the `type` parameter should be the
type of the element in the varray, for example:
vmstate_struct!(HPETState, timers, [0 .. num_timers], VMSTATE_HPET_TIMER,
BqlRefCell).with_version_id(0)
But this breaks current type check, because it checks t
On 3/11/25 10:10 AM, Shameer Kolothum wrote:
From: Nicolin Chen
If a vSMMU is configured as a accelerated one, HW IOTLB will be used
and all cache invalidation should be done to the HW IOTLB too, v.s.
the emulated iotlb. In this case, an iommu notifier isn't registered,
as the devices behind
This implementation provides emulation for the Xiangshan Kunminghu SoC,
including support for UART, CLINT, IMSIC, and APLIC devices.
More details can be found at
https://github.com/OpenXiangShan/XiangShan
Please note the following parameters when running the Xiangshan Kunminghu
machine:
1.`-m`: C
On Tue, Mar 18, 2025 at 05:36:03PM +0100, Peter Krempa wrote:
> From: Peter Krempa
>
> As no argument parsing is employed the script is hard to use and when
> running without arguments it blurbs:
>
> $ ./scripts/render_block_graph.py
> Traceback (most recent call last):
>File "/home/pipo/g
Shameer,
Hey,
On 3/11/25 10:10 AM, Shameer Kolothum wrote:
From: Nicolin Chen
Read the underlying SMMUv3 device info and set corresponding IDR
bits. We need at least one cold-plugged vfio-pci dev associated
with the smmuv3-accel instance to do this now. Hence fail if it
is not available.
T
Split out mmap_lock, et al from page-protection.h
to a new header.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
accel/tcg/internal-target.h| 1 +
include/exec/mmap-lock.h | 33 +
include/exec/page-protection.h | 22 ---
Jason,
Hey!
On 3/18/25 8:23 PM, Jason Gunthorpe wrote:
On Tue, Mar 18, 2025 at 05:22:51PM -0400, Donald Dutile wrote:
I agree with Eric that 'accel' isn't needed -- this should be
ascertained from the pSMMU that a physical device is attached to.
I seem to remember the point was made that we
在 2025/3/19 上午12:23, Peter Maydell 写道:
On Fri, 7 Mar 2025 at 02:42, Song Gao wrote:
For LoongArch th min tlb_ps is 12(4KB), for TLB code,
the tlb_ps may be 0,this may case UndefinedBehavior
Add a check-tlb_ps fuction to check tlb_ps,
to make sure the tlb_ps is avalablie. we check tlb_ps
when ge
On 3/18/25 21:21, Markus Armbruster wrote:
zhenwei pi writes:
Hi Markus,
Current code style seems buggy, I think the main reason is that the Error *errp
is not generated at right place. keyctl_pkey_XXX fails without new error,
qcrypto_akcipher_XXX fails with new error, but they are in th
Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source
high-performance RISC-V processor. More details can be found at
https://github.com/OpenXiangShan/XiangShan
Note:
The ISA extensions supported by the Xiangshan Kunminghu CPU are categorized
based on four RISC-V specifications: Volume I
Temporary variable ret is assigned at last line and return, it can
be removed and return directly.
Signed-off-by: Bibo Mao
Reviewed-by: Markus Armbruster
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/tcg/tlb_helper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff -
This patch set solves errors reported by coccinelle tool with commands:
spatch --sp-file scripts/coccinelle/*.cocci --dir target/loongarch/
spatch --sp-file scripts/coccinelle/*.cocci --dir hw/loongarch/
The main problem is that qemu should fail to run when feature is forced
to enabled however
In function virt_cpu_irq_init(), there is notification with ipi and extioi
interrupt controller for cpu creation. Local variable with error type is
used, however there is no check with its return value.
Here set dest error object with error_abort, rather than local variable, so
application will ab
For some paravirt KVM features, if user forces to enable it however
KVM does not support, qemu should fail to run and exit immediately,
rather than continue to run. Here set error message and return directly
in function kvm_arch_init_vcpu().
Fixes: 6edd2a9bec90 (target/loongarch/kvm: Implement Loo
In expression 1ULL << tlb_ps, left shifting by more than 63 bits has undefined
behavior.
The shift amount, tlb_ps, is as much as 64. check "tlb_ps >=64" to fix.
Resolves: Coverity CID 1593475
Fixes: d882c284a3 ("target/loongarch: check tlb_ps")
Suggested-by: Peter Maydell
Signed-off-by: Song G
On 3/18/25 14:32, Richard Henderson wrote:
This is include/system, so CONFIG_USER_ONLY will never be true.
Signed-off-by: Richard Henderson
---
include/system/qtest.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/system/qtest.h b/include/system/qtest.h
index 6c501b..84b1f8
On 3/18/25 17:42, Pierrick Bouvier wrote:
On 3/18/25 14:32, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/exec/icount.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/exec/icount.h b/include/exec/icount.h
index 4964987ae4..7a26b4
On Thu, Mar 13, 2025 at 4:27 PM ~yuming wrote:
>
> From: Yu-Ming Chang
>
> For privilege version 1.12 or newer, C always implies Zca. We can only
> check ext_zca to allow 16-bit aligned PC addresses. For older privilege
> versions, we only check C.
>
> Signed-off-by: Yu-Ming Chang
Please increm
On Wed, Mar 19, 2025 at 7:39 AM Richard Henderson
wrote:
>
> While RISCVCPUConfig.satp_mode is unused for user-only,
> this header is used from disas/riscv.h, whose users are
> only built once. The savings of 4 bytes isn't worth it.
>
> Reviewed-by: Pierrick Bouvier
> Signed-off-by: Richard Hend
On Tue, Mar 18, 2025 at 05:22:51PM -0400, Donald Dutile wrote:
> I agree with Eric that 'accel' isn't needed -- this should be
> ascertained from the pSMMU that a physical device is attached to.
I seem to remember the point was made that we don't actually know if
accel is possible, or desired, es
On Thu, Mar 13, 2025 at 5:23 AM Paolo Savini wrote:
>
> Adding reviewer information to the patch and rebasing on top of master.
>
> Previous versions:
>
> - v1:
> https://lore.kernel.org/all/20250129144435.82451-1-paolo.sav...@embecosm.com/
> - v2:
> https://lore.kernel.org/all/20250221155320.59
On Tue, Mar 11, 2025 at 4:18 PM Paolo Bonzini wrote:
>
>
>
> Il lun 10 mar 2025, 23:18 Alistair Francis ha scritto:
>>
>> On Tue, Mar 11, 2025 at 3:34 AM Paolo Bonzini wrote:
>> >
>> > On Fri, Mar 7, 2025 at 1:45 AM Alistair Francis
>> > wrote:
>> > > I'm not convinced that this is the thing t
Shameer,
Hi,
On 3/11/25 10:10 AM, Shameer Kolothum wrote:
From: Nicolin Chen
Inroduce an SMMUCommandBatch and some helpers to batch and issue the
Introduce
commands. Currently separate out TLBI commands and device cache commands
to avoid some errata on certain versions of SMMUs
On 3/18/25 17:15, Pierrick Bouvier wrote:
@@ -329,7 +331,39 @@ static bool translator_ld(CPUArchState *env,
DisasContextBase *db,
host = db->host_addr[1];
}
- memcpy(dest, host + (pc - base), len);
+ do_read:
+ /*
+ * Assume aligned reads should be atomic, if possible.
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, March 18, 2025 8:39 PM
> To: Troy Lee ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ;
> open list:ASPEED BMCs ; open list:All patches CC
> here
> Cc: Yunlin Tang
> Subject: Re: [PAT
On 3/18/25 17:02, Pierrick Bouvier wrote:
On 3/18/25 14:31, Richard Henderson wrote:
The implementation of cpu_mmu_index was split between cpu-common.h
and cpu-all.h, depending on CONFIG_USER_ONLY. We already have the
plumbing common to user and system mode. Using MMU_USER_IDX
requires the cpu
On 3/18/25 14:31, Richard Henderson wrote:
These routines are buggy in multiple ways:
- Use of target-endian loads, then a bswap that
depends on the host endiannness.
- A non-unwinding code load must set_helper_retaddr 1,
which is magic within adjust_signal_pc.
- cpu_ldq_code_m
On 3/18/25 16:52, Pierrick Bouvier wrote:
On 3/18/25 14:31, Richard Henderson wrote:
These routines are buggy in multiple ways:
- Use of target-endian loads, then a bswap that
depends on the host endiannness.
The code is very similar to do_ld*_mmu functions, so it's subtle to notice.
On 3/18/25 18:05, Richard Henderson wrote:
On 3/18/25 16:52, Pierrick Bouvier wrote:
On 3/18/25 14:31, Richard Henderson wrote:
These routines are buggy in multiple ways:
- Use of target-endian loads, then a bswap that
depends on the host endiannness.
The code is very similar to do_
On 3/18/25 14:31, Richard Henderson wrote:
The implementation of cpu_mmu_index was split between cpu-common.h
and cpu-all.h, depending on CONFIG_USER_ONLY. We already have the
plumbing common to user and system mode. Using MMU_USER_IDX
requires the cpu.h for a specific target, and so is restric
On 3/18/25 14:32, Richard Henderson wrote:
Poison CONFIG_USER_ONLY and CONFIG_SOFTMMU unless
the compilation unit is in specific_ss, libuser_ss,
or libsystem_ss. This is intended to prevent files
being incorrectly added to common_ss.
Remove #ifndef CONFIG_USER_ONLY / #error / #endif blocks.
All
On 3/18/25 14:31, Richard Henderson wrote:
We do not set CONFIG_SEMIHOSTING in
configs/targets/xtensa*-linux-user.mak.
Do not raise SIGILL for user-only unconditionally.
Signed-off-by: Richard Henderson
---
target/xtensa/translate.c | 24 +++-
1 file changed, 11 insertio
On 3/18/25 14:32, Richard Henderson wrote:
Split icount stuff from system/cpu-timers.h.
There are 17 files which only require icount.h, 7 that only
require cpu-timers.h, and 7 that require both.
Signed-off-by: Richard Henderson
---
include/exec/icount.h| 68 +++
On 3/18/25 14:32, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/exec/icount.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/exec/icount.h b/include/exec/icount.h
index 4964987ae4..7a26b40084 100644
--- a/include/exec/icount.h
+++
On 3/18/25 14:31, Richard Henderson wrote:
Some of the headers used require CONFIG_USER_ONLY.
Do not move vl.c, because it has other include dependencies
that are present in system_ss.
Signed-off-by: Richard Henderson
---
system/meson.build | 7 +--
1 file changed, 5 insertions(+), 2 del
On 3/18/25 14:31, Richard Henderson wrote:
Relatively few objects in qemu care about watchpoints, so split
out to a new header. Removes an instance of CONFIG_USER_ONLY
from hw/core/cpu.h.
Signed-off-by: Richard Henderson
---
include/exec/watchpoint.h | 41 ++
On 3/18/25 14:31, Richard Henderson wrote:
We do not set CONFIG_SEMIHOSTING in
configs/targets/mips*-linux-user.mak.
Signed-off-by: Richard Henderson
---
target/mips/cpu.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index b
On 3/18/25 14:31, Richard Henderson wrote:
Headers used by these files require CONFIG_USER_ONLY.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
plugins/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/plugins/meson.build b/plugins/meson
On 3/18/25 14:32, Richard Henderson wrote:
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them. The inlines
for user-only are unused.
Signed-off-by: Richard Henderson
---
include/hw/intc/armv7m_nvic.h | 14 --
1 file changed, 14 deleti
On 3/18/25 14:31, Richard Henderson wrote:
Cache the mmu index in DisasContextBase.
Perform the read on host endianness, which lets us
share code with the translator_ld fast path.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 1 +
accel/tcg/translator.c| 58 ++
On Tue, Mar 18, 2025 at 07:31:36PM +0100, Eric Auger wrote:
> Nevertheless I don't think anything prevents the acceleration granted
> device from also working with virtio/vhost devices for instance unless
> you unplug the existing infra.
If the accel mode is using something like vcmdq then it is n
On 3/18/25 14:31, Richard Henderson wrote:
Avoid testing CONFIG_USER_ONLY in semihost.h.
The only function that's required is semihosting_enabled.
Signed-off-by: Richard Henderson
---
include/semihosting/semihost.h | 29 ++---
semihosting/user.c | 15 +
On 3/18/25 14:31, Richard Henderson wrote:
Perform aligned atomic reads in translator_ld, if possible.
According to
https://lore.kernel.org/qemu-devel/20240607101403.1109-1-jim@sifive.com/
this is required for RISC-V Ziccif.
Signed-off-by: Richard Henderson
---
accel/tcg/translator.c |
Hi Lei,
On 3/18/2025 7:06 AM, Lei Yang wrote:
On Tue, Mar 18, 2025 at 10:15 AM Jason Wang wrote:
On Tue, Mar 18, 2025 at 9:55 AM Lei Yang wrote:
Hi Jonah
I tested this series with the vhost_vdpa device based on mellanox
ConnectX-6 DX nic and hit the host kernel crash. This problem can be
ea
These need to be per-target for 'abi_ptr'. Expand inline to
the *_data_ra api with ra == 0.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 123 ++--
accel/tcg/ldst_common.c.inc | 89 --
2
On Wed, Mar 19, 2025 at 7:36 AM Richard Henderson
wrote:
>
> Perform aligned atomic reads in translator_ld, if possible.
> According to
>
> https://lore.kernel.org/qemu-devel/20240607101403.1109-1-jim@sifive.com/
>
> this is required for RISC-V Ziccif.
Thanks Richard!!
>
> Signed-off-by: Ric
Some of the headers used require CONFIG_USER_ONLY.
Do not move vl.c, because it has other include dependencies
that are present in system_ss.
Signed-off-by: Richard Henderson
---
system/meson.build | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/system/meson.build b/sy
On 3/18/25 14:31, Richard Henderson wrote:
These routines are buggy in multiple ways:
- Use of target-endian loads, then a bswap that
depends on the host endiannness.
The code is very similar to do_ld*_mmu functions, so it's subtle to notice.
Was the endianness bug due to the fact we u
On 3/18/2025 2:14 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Sid Manning
Sent: Tuesday, March 18, 2025 1:34 PM
To: ltaylorsimp...@gmail.com; 'Brian Cain'
; qemu-devel@nongnu.org
Cc: richard.hender...@linaro.org; phi...@linaro.org; Matheus Bernardino
(QUIC) ; a...@re
On Friday, March 7, 2025 10:24:12 AM CET Christian Schoenebeck wrote:
> Three fixes for 9p server's v9fs_reclaim_fd() function:
>
> * Patch 1 fixes a concurrency issue.
>
> * Patch 2 fixes a file descriptor leak and optimizes overall latency. On a
> test
> machine with ~800,000 FIDs, this redu
Shameer,
Hi,
On 3/11/25 10:10 AM, Shameer Kolothum wrote:
From: Nicolin Chen
Allocate and associate a vDEVICE object for the Guest device
with the vIOMMU. This will help the kernel to do the
vSID --> sid translation whenever required (eg: device specific
invalidations).
Signed-off-by: Nicoli
Add a unit test to cover some patterns accepted by vmstate_of and
vmstate_struct macros, which correspond to the following C version
macros:
* VMSTATE_BOOL_V
* VMSTATE_U64
* VMSTATE_STRUCT_VARRAY_UINT8
* (no C version) MULTIPLY variant of VMSTATE_STRUCT_VARRAY_UINT32
* VMSTATE_ARRAY
Signed-o
Am 18.03.2025 um 11:58 hat ger...@altlinux.org geschrieben:
> From: Denis Rastyogin
>
> This error was discovered by fuzzing qemu-img.
>
> The qcow2_refresh_limits() is missing a check
> for the s->crypto pointer, which can lead to
> a null pointer dereference. This commit adds the necessary che
On 3/17/25 21:51, Pierrick Bouvier wrote:
To eliminate TARGET_AARCH64, we need to make various definitions common
between 32 and 64 bit Arm targets.
Added registers are used only by aarch64 code, and the only impact is on
the size of CPUARMState, and added zarray
(ARMVectorReg zarray[ARM_MAX_VQ *
We already have two subdirectories for which we need
to build files twice, for user vs system modes.
Move this handling to the top level.
This cannot be combined with user_ss or system_ss,
because the formulation has not been extended to support
configuration symbols.
Reviewed-by: Pierrick Bouvie
On 3/18/25 15:36, Richard Henderson wrote:
On 3/18/25 15:25, Pierrick Bouvier wrote:
On 3/18/25 15:21, Richard Henderson wrote:
On 3/18/25 15:16, Pierrick Bouvier wrote:
This doesn't make any sense to me. CPU_INCLUDE is defined within the very file
that
you're trying to include by avoiding "
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