Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source
high-performance RISC-V processor. More details can be found at
https://github.com/OpenXiangShan/XiangShan
Note:
The ISA extensions supported by the Xiangshan Kunminghu CPU are categorized
based on four RISC-V specifications: Volume I: Unprivileged Architecture,
Volume II: Privileged Architecture, AIA, and RVA23. The extensions within
each category are organized according to the chapter order in the
specifications.
Signed-off-by: Yu Hu <h...@bosc.ac.cn>
Signed-off-by: Ran Wang <wang...@bosc.ac.cn>
Signed-off-by: Borong Huang <huangbor...@bosc.ac.cn>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 72 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 73 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 4cfdb74891..f2908939e7 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -53,6 +53,7 @@
#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
#define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon")
#define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nanhu")
+#define TYPE_RISCV_CPU_XIANGSHAN_KMH
RISCV_CPU_TYPE_NAME("xiangshan-kunminghu")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 09ded6829a..a076d9dc0c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -697,6 +697,76 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
#endif
}
+static void rv64_xiangshan_kmh_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+
+ riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU | RVH | RVV);
+ env->priv_ver = PRIV_VERSION_1_13_0;
+
+ /* Enable ISA extensions */
+ cpu->cfg.mmu = true;
+ cpu->cfg.pmp = true;
+
+ /*
+ * The RISC-V Instruction Set Manual: Volume I
+ * Unprivileged Architecture
+ */
+ cpu->cfg.ext_zicntr = true;
+ cpu->cfg.ext_zihpm = true;
+ cpu->cfg.ext_zihintntl = true;
+ cpu->cfg.ext_zihintpause = true;
+ cpu->cfg.ext_zimop = true;
+ cpu->cfg.ext_zcmop = true;
+ cpu->cfg.ext_zicond = true;
+ cpu->cfg.ext_zawrs = true;
+ cpu->cfg.ext_zacas = true;
+ cpu->cfg.ext_zfh = true;
+ cpu->cfg.ext_zfa = true;
+ cpu->cfg.ext_zcb = true;
+ cpu->cfg.ext_zbc = true;
+ cpu->cfg.ext_zvfh = true;
+ cpu->cfg.ext_zkn = true;
+ cpu->cfg.ext_zks = true;
+ cpu->cfg.ext_zkt = true;
+ cpu->cfg.ext_zvbb = true;
+ cpu->cfg.ext_zvkt = true;
+
+ /*
+ * The RISC-V Instruction Set Manual: Volume II
+ * Privileged Architecture
+ */
+ cpu->cfg.ext_smstateen = true;
+ cpu->cfg.ext_smcsrind = true;
+ cpu->cfg.ext_sscsrind = true;
+ cpu->cfg.ext_svnapot = true;
+ cpu->cfg.ext_svpbmt = true;
+ cpu->cfg.ext_svinval = true;
+ cpu->cfg.ext_sstc = true;
+ cpu->cfg.ext_sscofpmf = true;
+ cpu->cfg.ext_ssdbltrp = true;
+ cpu->cfg.ext_ssnpm = true;
+ cpu->cfg.ext_smnpm = true;
+ cpu->cfg.ext_smmpm = true;
+ cpu->cfg.ext_sspm = true;
+ cpu->cfg.ext_supm = true;
+
+ /* The RISC-V Advanced Interrupt Architecture */
+ cpu->cfg.ext_smaia = true;
+ cpu->cfg.ext_ssaia = true;
+
+ /* RVA23 Profiles */
+ cpu->cfg.ext_zicbom = true;
+ cpu->cfg.ext_zicbop = true;
+ cpu->cfg.ext_zicboz = true;
+ cpu->cfg.ext_svade = true;
+
+#ifndef CONFIG_USER_ONLY
+ set_satp_mode_max_supported(cpu, VM_1_10_SV48);
+#endif
+}
+
#ifdef CONFIG_TCG
static void rv128_base_cpu_init(Object *obj)
{
@@ -3261,6 +3331,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64,
rv64_veyron_v1_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
MXL_RV64,
rv64_xiangshan_nanhu_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_KMH,
+ MXL_RV64,
rv64_xiangshan_kmh_cpu_init),
#ifdef CONFIG_TCG
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128,
rv128_base_cpu_init),
#endif /* CONFIG_TCG */
--
2.34.1
