Shameer,
Hey,
On 3/11/25 10:10 AM, Shameer Kolothum wrote:
From: Nicolin Chen <nicol...@nvidia.com>
Read the underlying SMMUv3 device info and set corresponding IDR
bits. We need at least one cold-plugged vfio-pci dev associated
with the smmuv3-accel instance to do this now. Hence fail if it
is not available.
ToDo: The above requirement will be relaxed in future when we add
support in the kernel.
Signed-off-by: Nicolin Chen <nicol...@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
---
hw/arm/smmuv3-accel.c | 104 ++++++++++++++++++++++++++++++++++
hw/arm/trace-events | 1 +
include/hw/arm/smmuv3-accel.h | 2 +
3 files changed, 107 insertions(+)
diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
index 09be838d22..fb08e1d66b 100644
--- a/hw/arm/smmuv3-accel.c
+++ b/hw/arm/smmuv3-accel.c
@@ -15,6 +15,96 @@
#include "smmuv3-internal.h"
+static int
+smmuv3_accel_dev_get_info(SMMUv3AccelDevice *accel_dev, uint32_t *data_type,
+ uint32_t data_len, void *data)
+{
+ uint64_t caps;
+
+ if (!accel_dev || !accel_dev->idev) {
+ return -ENOENT;
+ }
+
+ return !iommufd_backend_get_device_info(accel_dev->idev->iommufd,
+ accel_dev->idev->devid,
+ data_type, data,
+ data_len, &caps, NULL);
+}
+
+static void smmuv3_accel_init_regs(SMMUv3AccelState *s_accel)
+{
+ SMMUv3State *s = ARM_SMMUV3(s_accel);
+ SMMUv3AccelDevice *accel_dev;
+ uint32_t data_type;
+ uint32_t val;
+ int ret;
+
+ if (!s_accel->viommu || QLIST_EMPTY(&s_accel->viommu->device_list)) {
+ error_report("At least one cold-plugged vfio-pci is required for
smmuv3-accel!");
+ exit(1);
+ }
+
+ accel_dev = QLIST_FIRST(&s_accel->viommu->device_list);
+ if (accel_dev->info.idr[0]) {
+ info_report("reusing the previous hw_info");
+ goto out;
+ }
+
+ ret = smmuv3_accel_dev_get_info(accel_dev, &data_type,
+ sizeof(accel_dev->info), &accel_dev->info);
+ if (ret) {
+ error_report("failed to get SMMU device info");
+ return;
+ }
+
+ if (data_type != IOMMU_HW_INFO_TYPE_ARM_SMMUV3) {
+ error_report("Wrong data type (%d)!", data_type);
+ return;
+ }
+
+out:
+ trace_smmuv3_accel_get_device_info(accel_dev->info.idr[0],
+ accel_dev->info.idr[1],
+ accel_dev->info.idr[3],
+ accel_dev->info.idr[5]);
+
+ val = FIELD_EX32(accel_dev->info.idr[0], IDR0, BTM);
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, BTM, val);
+ val = FIELD_EX32(accel_dev->info.idr[0], IDR0, ATS);
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, val);
+ val = FIELD_EX32(accel_dev->info.idr[0], IDR0, ASID16);
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ASID16, val);
+ val = FIELD_EX32(accel_dev->info.idr[0], IDR0, TERM_MODEL);
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TERM_MODEL, val);
+ val = FIELD_EX32(accel_dev->info.idr[0], IDR0, STALL_MODEL);
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, val);
+ val = FIELD_EX32(accel_dev->info.idr[0], IDR0, STLEVEL);
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STLEVEL, val);
+
+ val = FIELD_EX32(accel_dev->info.idr[1], IDR1, SIDSIZE);
+ s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SIDSIZE, val);
+ val = FIELD_EX32(accel_dev->info.idr[1], IDR1, SSIDSIZE);
+ s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, val);
+
+ val = FIELD_EX32(accel_dev->info.idr[3], IDR3, HAD);
+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, val);
+ val = FIELD_EX32(accel_dev->info.idr[3], IDR3, RIL);
+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, val);
+ val = FIELD_EX32(accel_dev->info.idr[3], IDR3, BBML);
+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, val);
+
+ val = FIELD_EX32(accel_dev->info.idr[5], IDR5, GRAN4K);
+ s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, val);
+ val = FIELD_EX32(accel_dev->info.idr[5], IDR5, GRAN16K);
+ s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN16K, val);
+ val = FIELD_EX32(accel_dev->info.idr[5], IDR5, GRAN64K);
+ s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, val);
+ val = FIELD_EX32(accel_dev->info.idr[5], IDR5, OAS);
+ s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, val);
+
+ /* FIXME check iidr and aidr registrs too */
+}
+
static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *s, SMMUPciBus *sbus,
PCIBus *bus, int devfn)
{
@@ -484,11 +574,25 @@ static void smmu_accel_realize(DeviceState *d, Error
**errp)
bs->unset_iommu_device = smmuv3_accel_unset_iommu_device;
}
+static void smmuv3_accel_reset_hold(Object *obj, ResetType type)
+{
+ SMMUv3AccelState *s = ARM_SMMUV3_ACCEL(obj);
+ SMMUv3AccelClass *c = ARM_SMMUV3_ACCEL_GET_CLASS(s);
+
+ if (c->parent_phases.hold) {
+ c->parent_phases.hold(obj, type);
+ }
+ smmuv3_accel_init_regs(s);
+}
reset has to be moved from hold to exit phase....
Eric recently posted a fix for this issue in upstream.
... and if accel was just a feature of the common smmuv3 support, this reset
wouldn't be needed...
+
static void smmuv3_accel_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
SMMUv3AccelClass *c = ARM_SMMUV3_ACCEL_CLASS(klass);
+ resettable_class_set_parent_phases(rc, NULL, smmuv3_accel_reset_hold, NULL,
+ &c->parent_phases);
device_class_set_parent_realize(dc, smmu_accel_realize,
&c->parent_realize);
dc->hotpluggable = false;
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index cd2eac31c2..c7a7e58291 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -62,6 +62,7 @@ smmu_reset_exit(void) ""
smmuv3_accel_set_iommu_device(int devfn, uint32_t sid) "devfn=0x%x (sid=0x%x)"
smmuv3_accel_unset_iommu_device(int devfn, uint32_t sid) "devfn=0x%x
(sid=0x%x"
smmuv3_accel_install_nested_ste(uint32_t sid, uint64_t ste_1, uint64_t ste_0) "sid=%d
ste=%"PRIx64":%"PRIx64
+smmuv3_accel_get_device_info(uint32_t idr0, uint32_t idr1, uint32_t idr3, uint32_t idr5)
"idr0=0x%x idr1=0x%x idr3=0x%x idr5=0x%x"
# strongarm.c
strongarm_uart_update_parameters(const char *label, int speed, char parity, int
data_bits, int stop_bits) "%s speed=%d parity=%c data=%d stop=%d"
diff --git a/include/hw/arm/smmuv3-accel.h b/include/hw/arm/smmuv3-accel.h
index 58e68534c0..9e30d7d351 100644
--- a/include/hw/arm/smmuv3-accel.h
+++ b/include/hw/arm/smmuv3-accel.h
@@ -52,6 +52,7 @@ typedef struct SMMUv3AccelDevice {
SMMUViommu *viommu;
SMMUVdev *vdev;
AddressSpace as_sysmem;
+ struct iommu_hw_info_arm_smmuv3 info;
QLIST_ENTRY(SMMUv3AccelDevice) next;
} SMMUv3AccelDevice;
@@ -68,6 +69,7 @@ struct SMMUv3AccelClass {
/*< public >*/
DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
};
#endif /* HW_ARM_SMMUV3_ACCEL_H */
In general, I would move this common code stuff at the front of the patch
series... just gathering registers, capabilities, etc.
- Don
