On 12/03/2025 06.17, Nicholas Piggin wrote:
Assets are uniquely identified by human-readable-ish url, so make an
AssetError exception class that prints url with error message.
A property 'transient' is used to capture whether the client may retry
or try again later, or if it is a serious and lik
On 12/03/2025 06.17, Nicholas Piggin wrote:
If the server provides a Content-Length header, use that to verify the
size of the downloaded file. This catches cases where the connection
terminates early, and gives the opportunity to retry. Without this, the
checksum will likely mismatch and fail wi
On 12/03/2025 06.17, Nicholas Piggin wrote:
Currently the fetch code does not fail gracefully when retry limit is
exceeded, it just falls through the loop with no file, which ends up
hitting other errors.
In preparation for adding more cases where a download gets retried,
add an explicit check f
Add index entry for LoongArch system and do some small modification
with LoongArch document with rst syntax.
Signed-off-by: Bibo Mao
---
docs/system/loongarch/virt.rst | 31 ++-
docs/system/target-loongarch.rst | 19 +++
docs/system/targets.rst
On 12/03/2025 04.44, Bibo Mao wrote:
Add cpu hotplug testcase support for LoongArch system, it passes to
run with command "make check-qtest-loongarch64" as following:
qemu:qtest+qtest-loongarch64 / qtest-loongarch64/cpu-plug-test OK 0.38s 1
subtests passed
Signed-off-by: Bibo Mao
---
v1 ...
When POWER10 CPU was made as default, we missed keeping POWER9 as
default for older pseries releases (pre-10.0) at that time.
This caused breakge in default cpu evaluation for older pseries
machines and hence this fix.
Fixes: 51113013f3 ("ppc/spapr: change pseries machine default to POWER10 CPU")
On Wed Mar 12, 2025 at 12:11 AM AEST, Daniel P. Berrangé wrote:
> On Tue, Mar 11, 2025 at 02:55:25PM +0100, Thomas Huth wrote:
>> On 11/03/2025 14.37, Daniel P. Berrangé wrote:
>> > On Tue, Mar 11, 2025 at 11:13:26PM +1000, Nicholas Piggin wrote:
>> > > The NetBSD archive is currently failing part-
On 3/11/2025 8:54 PM, Alejandro Jimenez wrote:
The size mask currently encompasses reserved bits [11:9]. Extract only the
corrects bits encoding size (i.e. [8:0]).
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
---
hw/i386/a
Currently the fetch code does not fail gracefully when retry limit is
exceeded, it just falls through the loop with no file, which ends up
hitting other errors.
In preparation for adding more cases where a download gets retried,
add an explicit check for retry limit exceeded.
Signed-off-by: Nicho
Assets are uniquely identified by human-readable-ish url, so make an
AssetError exception class that prints url with error message.
A property 'transient' is used to capture whether the client may retry
or try again later, or if it is a serious and likely permanent error.
This is used to retain th
Continuing discussion from
https://lore.kernel.org/qemu-devel/20250311131327.903329-1-npig...@gmail.com/
I added a basic short-download detection, cleaned up download retry
failure, and added an AssetError class that can help us be a bit
smarter about what to do with failures. That's extended to
Hi,
Thank you for the clarification. Regarding the last time
"Stoptrigger might be a better fit for what you want to do, and instead of
exiting, you want to resume emulation after N insn. The function
qemu_clock_advance_virtual_time() can only be used to move the time forward,
and you can not
Hi Alejandro,
On 3/11/2025 8:54 PM, Alejandro Jimenez wrote:
The DTE validation method verifies that all bits in reserved DTE fields are
unset. Update them according to the latest definition available in AMD I/O
Virtualization Technology (IOMMU) Specification - Section 2.2.2.1 Device
Table Entry
On Tue, Feb 18, 2025 at 7:43 AM Stefan Hajnoczi wrote:
>
> On Mon, Feb 17, 2025 at 05:40:04PM +0100, Albert Esteve wrote:
> > Add SHMEM_MAP/UNMAP requests to vhost-user to
> > handle VIRTIO Shared Memory mappings.
> >
> > This request allows backends to dynamically map
> > fds into a VIRTIO Shared
Add cpu hotplug testcase support for LoongArch system, it passes to
run with command "make check-qtest-loongarch64" as following:
qemu:qtest+qtest-loongarch64 / qtest-loongarch64/cpu-plug-test OK 0.38s 1
subtests passed
Signed-off-by: Bibo Mao
---
v1 ... v2:
1. Call test function add_loongar
On Tue, Mar 11, 2025 at 02:27:14PM +0100, Laurent Vivier wrote:
> Add a chapter to explain how to use passt(1) instead of '-net user'.
> passt(1) can be connected to QEMU using UNIX socket or vhost-user.
> With vhost-user, migration of the VM is allowed and internal state of
> passt(1) is transfere
To support AST2700 A1, some registers of the INTC(CPU Die) support one input
pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC
controller code for better clarity and consistency in naming conventions.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
include/h
On Sun, 9 Mar 2025 at 19:01, Philippe Mathieu-Daudé wrote:
> On 28/2/25 18:48, Peter Maydell wrote:
> > --- a/hw/net/smc91c111.c
> > +++ b/hw/net/smc91c111.c
> > @@ -22,6 +22,13 @@
> >
> > /* Number of 2k memory pages available. */
> > #define NUM_PACKETS 4
> > +/*
> > + * Maximum size of a d
On 2025/03/10 21:05, Dmitry Osipenko wrote:
From: Alex Bennée
This attempts to tidy up the VirtIO GPU documentation to make the list
of requirements clearer. There are still a lot of moving parts and the
distros have some catching up to do before this is all handled
automatically.
Signed-off-b
Peter Xu writes:
> On Fri, Mar 07, 2025 at 04:06:17PM -0300, Fabiano Rosas wrote:
>> > I never tried vsock, would it be used in any use case?
>> >
>>
>> I don't know, I'm going by what's in the code.
>>
>> > It seems to be introduced by accident in 72a8192e225cea, but I'm not sure.
>> > Maybe t
From: "Maciej S. Szmigiero"
A new function multifd_queue_device_state() is provided for device to queue
its state for transmission via a multifd channel.
Reviewed-by: Peter Xu
Signed-off-by: Maciej S. Szmigiero
Link:
https://lore.kernel.org/qemu-devel/ebd55768d3e5fecb5eb3f197bad9c0c07e5bc084.
To support AST2700 A1, some registers of the INTC(CPU Die) support one input
pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC
controller code for better clarity and consistency in naming conventions.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
include/h
This method adds the options/preamble to each definition block. Notably,
:since: and :ifcond: are added, as are any "special features" such as
:deprecated: and :unstable:.
If conditionals, if attached to special features, are currently
unhandled in this patch and will be addressed at a future date
Support asynchronous fencing feature of virglrenderer. It allows Qemu to
handle fence as soon as it's signalled instead of periodically polling
the fence status. This feature is required for enabling DRM context
support in Qemu because legacy fencing mode isn't supported for DRM
contexts in virglre
John Snow writes:
> This is the true top-level processor for the new transmogrifier;
> responsible both for generating the intermediate rST and then running
> the nested parse on that generated document to produce the final
> docutils tree that is then - very finally - postprocessed by sphinx for
On 2025/3/10 15:13, Cédric Le Goater wrote:
> Tomita,
>
> On 3/7/25 19:37, Tomita Moeko wrote:
>> On 2025/3/7 6:49, Alex Williamson wrote:
>>> On Fri, 7 Mar 2025 02:01:27 +0800
>>> Tomita Moeko wrote:
>>>
So far, IGD-specific quirks all require enabling legacy mode, which is
toggled by
On 3/9/25 21:58, Pierrick Bouvier wrote:
This function is used by system/physmem.c will be turn into common code
in next commit.
Signed-off-by: Pierrick Bouvier
---
include/system/kvm.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
is already included by "system/kvm.h" in the next line.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Reviewed-by: Cédric Le Goater
Reviewed-by: Eric Auger
Message-Id: <20250307180337.14811-3-phi...@linaro.org>
---
hw/vfio/spapr.c | 3 ---
On 3/6/25 11:38, Jamin Lin wrote:
Added a new method "start_ast2700_test" to the "AST2x00MachineSDK" class and
this method centralizes the logic for starting the AST2700 test, making it
reusable for different test cases.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
In MCD, core-specific operations require an open connection to the core.
This commit implements the necessary operations to open and close the
connection to cores.
Signed-off-by: Mario Fleischmann
---
mcd/mcdserver.c | 176 ---
mcd/mcdstub_qapi.c| 11
From: John Snow
Sphinx prior to v4.0 uses different classes for rendering elements of
documentation objects; add some compatibility classes to use the right
node classes conditionally.
Signed-off-by: John Snow
Message-ID: <20250311034303.75779-10-js...@redhat.com>
Acked-by: Markus Armbruster
S
Mostly revert commit c80cafa0c73 ("system: Add qemu_init_arch_modules")
but using target_name() instead of the target specific 'TARGET_NAME'
definition.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250305005225.95051-3-phi...@linaro.org>
---
include/system
On Fri, Mar 07, 2025 at 11:16:31PM +0100, Kevin Wolf wrote:
> For block drivers that don't advertise FUA support, we already call
> bdrv_co_flush(), which considers BDRV_O_NO_FLUSH. However, drivers that
> do support FUA still see the FUA flag with BDRV_O_NO_FLUSH and get the
> associated performan
On 3/10/25 11:35 AM, Rorie Reyes wrote:
Register an event notifier handler to process AP configuration
change events by queuing the event and generating a CRW to let
the guest know its AP configuration has changed
Signed-off-by: Rorie Reyes
LGTM:
Reviewed-by: Anthony Krowiak
---
hw/v
On Mon, Mar 10, 2025 at 03:12:05PM -0400, Peter Xu wrote:
> On Sun, Mar 09, 2025 at 09:15:00PM -0400, Manish Mishra wrote:
> > We allocate extra metadata SKBs in case of a zerocopy send. This metadata
> > memory is accounted for in the OPTMEM limit. If there is any error while
> > sending zerocopy
While the (intno << shift) expression is correct for indexing the IDT based on
whether Long Mode is active, the error code itself was unchanged with AMD64,
and is still the index with 3 bits of metadata in the bottom.
Found when running a Xen unit test, all under QEMU. The unit test objected to
b
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
On Tue Mar 11, 2025 at 11:37 PM AEST, Daniel P. Berrangé wrote:
> On Tue, Mar 11, 2025 at 11:13:26PM +1000, Nicholas Piggin wrote:
>> The NetBSD archive is currently failing part-way through downloads,
>> which results in no clean HTTP error but a short transfer and checksum
>> error. This is treat
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
Add reset support with ipi object, register reset callback and clear
internal registers when virt machine resets.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 29 +
include/hw/intc/loongarch_ipi.h | 1 +
2 files changed, 30 insertions(+)
diff --git
On 3/10/25 08:17, Richard Henderson wrote:
On 3/9/25 21:58, Pierrick Bouvier wrote:
They are now accessible through exec/memory.h instead, and we make sure
all variants are available for common or target dependent code.
...
diff --git a/include/exec/memory_ldst.h.inc b/include/exec/memory_ldst
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
In MCD, all accesses to register or memory are issued over transaction lists.
This commit implements three types of transactions:
* register access
* logical memory access (with MMU)
* physical memory access (no MMU)
Signed-off-by: Mario Fleischmann
---
mcd/libmcd_qapi.c | 128
Nabih,
On 3/6/25 01:04, Nabih Estefan wrote:
Setting BIT6 in VGA0 SCRATCH register will indicate that the ddr traning
is done, therefore skipping the u-boot-spl dram_init() process.
Signed-off-by: Jamin Lin
Signed-off-by: Troy Lee
Reviewed-by: Cédric Le Goater
Tested-by: Nabih Estefan
Th
From: John Snow
This class is a generic, top-level directive for documenting some kind
of QAPI thingamajig that we expect to go into the Index. This class
doesn't do much by itself, and it isn't yet associated with any
particular directive.
handle_signature(), _object_hierarchy_parts() and _toc_
Hi Zoltan,
On 3/10/25 06:23, BALATON Zoltan wrote:
On Sun, 9 Mar 2025, Pierrick Bouvier wrote:
The main goal of this series is to be able to call any memory ld/st function
from code that is *not* target dependent.
Why is that needed?
this series belongs to the "single binary" topic, where
Fixes: ca056f4499c2 (Python: Drop support for Python 3.7)
Signed-off-by: Markus Armbruster
Message-ID: <20250227080757.3978333-2-arm...@redhat.com>
Reviewed-by: Daniel P. Berrangé
---
docs/about/build-platforms.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/about/bu
On Tue, Mar 11, 2025 at 08:08:02PM +, Daniel P. Berrangé wrote:
> On Tue, Mar 11, 2025 at 03:57:35PM -0400, Peter Xu wrote:
> > On Tue, Mar 11, 2025 at 03:33:23PM +, Daniel P. Berrangé wrote:
> > > On Tue, Mar 11, 2025 at 11:20:50AM -0400, Peter Xu wrote:
> > > > On Tue, Mar 11, 2025 at 08:
On Tue, Mar 11, 2025 at 02:10:34PM +, Shameer Kolothum wrote:
> @@ -30,6 +32,185 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState
> *s, SMMUPciBus *sbus,
> return accel_dev;
> }
>
> +static bool
> +smmuv3_accel_dev_attach_viommu(SMMUv3AccelDevice *accel_dev,
> +
On Mon, 10 Mar 2025, Philippe Mathieu-Daudé wrote:
Add MemoryRegionOps as a class property. For now it is only
used by TYPE_IMX_USDHC.
Otherwise the default remains in little endian.
I still don't see why you need to do this via the class and not just set
it init or realize as it's done alread
In preparation to make @dump-skeys command generic,
extract s390_qmp_dump_skeys() out of qmp_dump_skeys().
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/s390x/storage-keys.h | 1 +
hw/s390x/s390-skeys.c | 7 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/i
On Tue, 11 Mar 2025, Philippe Mathieu-Daudé wrote:
All instances of TYPE_IMX_USDHC set vendor=SDHCI_VENDOR_IMX.
No need to special-case it.
Typo in subject. It's actually SDHCI_VENDOR_IMX which is removed by this
patch.
Regards,
BALATON Zoltan
Signed-off-by: Philippe Mathieu-Daudé
Reviewe
On 3/11/25 02:50, Saanjh Sengupta wrote:
Hi,
I have a couple of questions:
1.
When I use the libstoptrigger.so: in that case the QEMU 's emulation
stops after executing the defined number of instructions. Post this,
the whole QEMU terminates. And while using the libips.so I am
On Tue, Mar 11, 2025 at 02:10:33PM +, Shameer Kolothum wrote:
> diff --git a/include/hw/arm/smmuv3-accel.h b/include/hw/arm/smmuv3-accel.h
> index 56fe376bf4..86c0523063 100644
> --- a/include/hw/arm/smmuv3-accel.h
> +++ b/include/hw/arm/smmuv3-accel.h
> @@ -16,6 +16,10 @@
> #define TYPE_ARM_S
In linux-user/arm/cpu_loop.c we define a full set of get/put
macros for both code and data (since the endianness handling
is different between the two). However the only one we actually
use is get_user_code_u32(). Remove the rest.
We leave a comment noting how data-side accesses should be handled
Newer Arm CPUs need not implement AArch32 at all exception levels
(and Armv9 forbids implementing AArch32 at any EL except EL0).
All our current CPU models implement both AArch32 and AArch64
at every exception levels, so we currently get away with failing
to enforce that the guest isn't trying to d
On 3/9/25 00:09, Philippe Mathieu-Daudé wrote:
In order to be able to check whether a QOM type has been
registered, introduce the type_is_registered() helper.
Signed-off-by: Philippe Mathieu-Daudé
FWIW,
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
include/qom/object.h | 8
On 3/10/25 09:28, Pierrick Bouvier wrote:
Hi Zoltan,
On 3/10/25 06:23, BALATON Zoltan wrote:
On Sun, 9 Mar 2025, Pierrick Bouvier wrote:
The main goal of this series is to be able to call any memory ld/st function
from code that is *not* target dependent.
Why is that needed?
this series b
From: John Snow
Add the ability to resolve cross-references using the `any`
cross-reference syntax. Adding QAPI-specific cross-reference roles will
be added in a forthcoming commit, and will share the same find_obj()
helper.
(There's less code needed for the generic cross-reference resolver, so
Fields of SysBusDevice must only be accessed with the BQL taken. Add
a wrapper that verifies that.
Signed-off-by: Paolo Bonzini
---
rust/hw/timer/hpet/src/hpet.rs | 4 +---
rust/qemu-api/src/sysbus.rs| 12
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/rust/hw
From: "Maciej S. Szmigiero"
Add a hw_compat entry for recently added x-migration-multifd-transfer VFIO
property.
Reviewed-by: Cédric Le Goater
Signed-off-by: Maciej S. Szmigiero
Link:
https://lore.kernel.org/qemu-devel/92c354f0457c152d1f267cc258c6967fff551cb1.1741124640.git.maciej.szmigi...@o
On 6/3/25 08:26, Thomas Huth wrote:
On 05/03/2025 17.59, Pierrick Bouvier wrote:
On 3/5/25 07:39, Philippe Mathieu-Daudé wrote:
Introduce an API to get information specific to a binary
from the binary name (argv[0]).
Initialize it from qemu_init() on system emulation.
What we want here is m
We are trying to unify all qemu-system-FOO to a single binary.
In order to do that we need to remove QAPI target specific code.
Introduce the TYPE_DUMP_SKEYS_INTERFACE type which provide the
qmp_dump_skeys() callback, have it implemented on the CCW machine.
Machines not supporting this interface r
On Tue, Mar 11, 2025 at 02:10:29PM +, Shameer Kolothum wrote:
> Allow cold-plug smmuv3-accel to virt If the machine wide smmuv3
> is not specified.
>
> No FDT support is added for now.
>
> Signed-off-by: Shameer Kolothum
> ---
> hw/arm/virt.c | 12
> hw/core/sysbus-fdt.
On Tue, Mar 11, 2025 at 02:10:28PM +, Shameer Kolothum wrote:
> +/*
> + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd
> + * Copyright (C) 2025 NVIDIA
+ * Copyright (C) 2025 NVIDIA CORPORATION & AFFILIATES
> + * Written by Nicolin Chen, Shameer Kolothum
(Thanks for adding my name!)
On Tue, Mar 11, 2025 at 03:57:35PM -0400, Peter Xu wrote:
> On Tue, Mar 11, 2025 at 03:33:23PM +, Daniel P. Berrangé wrote:
> > On Tue, Mar 11, 2025 at 11:20:50AM -0400, Peter Xu wrote:
> > > On Tue, Mar 11, 2025 at 08:13:16AM +, Daniel P. Berrangé wrote:
> > > > On Mon, Mar 10, 2025 at 04:
Defining functions allows to use them from common code, by not depending
on TARGET_BIG_ENDIAN.
Remove previous macros from exec/cpu-all.h.
By moving them out of cpu-all.h, we'll be able to break dependency on
cpu.h for memory related functions coming in next commits.
Reviewed-by: Richard Henderson
Will allow to make system/memory.c common later.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/memory.h | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index da21e9150b5..069021
The main goal of this series is to be able to call any memory ld/st function
from code that is *not* target dependent. As a positive side effect, we can
turn related system compilation units into common code.
The first 5 patches remove dependency of memory API to cpu headers and remove
dependency
Needed so compilation units including it can be common.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/memory-internal.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
index 100c1237ac2..b729f
Only system/physmem.c and system/memory.c use those functions, so we can
move then to internal header.
Signed-off-by: Pierrick Bouvier
---
include/exec/memory-internal.h | 19 +++
include/exec/memory.h | 18 --
2 files changed, 19 insertions(+), 18 deleti
Define acpi_tables / acpi_tables_len stubs, then replace the
compile-time CONFIG_ACPI check in fw_cfg.c by a runtime one.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Ani Sinha
Message-Id: <20250307223949.54040-4-phi...@linaro.org>
---
hw/acpi/acpi-stub.c | 3 +++
hw/i386/fw_cfg.c| 8
Those functions are used by system/physmem.c, and are called only if
xen is enabled (which happens only if CONFIG_XEN is not set).
So we can crash in case those are called.
Acked-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/xen/xen_stubs.c | 56 +
They are now accessible through exec/memory.h instead, and we make sure
all variants are available for common or target dependent code.
Move stl_phys_notdirty function as well.
Cached endianness agnostic version rely on st/ld*_p, which is available
through tswap.h.
Reviewed-by: Richard Henderson
They are now accessible through exec/memory.h instead, and we make sure
all variants are available for common or target dependent code.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 12
include/exec/memory_ldst.h.inc | 4
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
system/ioport.c| 1 -
system/meson.build | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/system/ioport.c b/system/ioport.c
index 55c2a752396..89daae9d602 100644
--- a/system/ioport.c
+++ b/system/ioport.
On 3/9/25 12:09 AM, Philippe Mathieu-Daudé wrote:
> These files depend on the VFIO symbol in their Kconfig
> definition. They don't rely on target specific definitions,
> move them to system_ss[] to build them once.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Pierrick Bouvier
> R
Previous commit changed files relying transitively on it.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/exec-all.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index dd5c40f2233..19b0eda44a7 100644
--- a/i
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/ram_addr.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index 7c011fadd11..098fccb5835 100644
--- a/include/exec/ram_addr.h
+++ b/inclu
we'll use it in system/memory.c.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/memory.h | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 069021ac3ff..70177304a92 100644
-
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
system/memory.c| 17 +
system/meson.build | 2 +-
2 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/system/memory.c b/system/memory.c
index 4c829793a0a..eddd21a6cdb 100644
--- a/system/memory.c
Needed so compilation units including it can be common.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/ram_addr.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index 3d8df4edf15..7c011fadd
On Tue, 4 Mar 2025 18:37:47 +
Suravee Suthikulpanit wrote:
> The QEMU-emulated AMD IOMMU PCI device is implemented based on the AMD I/O
> Virtualization Technology (IOMMU) Specification [1]. The PCI id for this
> device is platform-specific.
>
> Currently, the QEMU-emulated AMD IOMMU device
On Mon, Mar 10, 2025 at 15:33:02 +0100, Kevin Wolf wrote:
> Am 13.02.2025 um 19:00 hat Stefan Hajnoczi geschrieben:
> > Allow virtio-scsi virtqueues to be assigned to different IOThreads. This
> > makes it possible to take advantage of host multi-queue block layer
> > scalability by assigning virtq
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
system/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/system/meson.build b/system/meson.build
index c83d80fa248..9d0b0122e54 100644
--- a/system/meson.build
+++ b/system/meson.build
@@ -2,7 +2,6 @
This function is used by system/physmem.c will be turn into common code
in next commit.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/system/kvm.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/system/kvm.h b/include/system/kvm.h
i
Add cache topology to PPTT table. With this patch, both ACPI PPTT table
and device tree will represent the same cache topology given users
input.
Signed-off-by: Alireza Sanaee
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
hw/acpi/aml-build.c| 205 +++
From: Jiqian Chen
In PVH dom0, when passthrough a device to domU, QEMU code
xen_pt_realize->xc_physdev_map_pirq wants to use gsi, but in current codes
the gsi number is got from file /sys/bus/pci/devices//irq, that is
wrong, because irq is not equal with gsi, they are in different spaces, so
pirq
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/tcg/tcg-op.h | 1 +
target/ppc/helper_regs.h | 2 ++
hw/ppc/spapr_nested.c | 1 +
hw/sh4/sh7750.c| 1 +
page-vary-target.c | 2 +-
target/riscv/bitmanip_helper.c | 2 +-
On 3/9/25 21:58, Pierrick Bouvier wrote:
This is needed for next commits (especially when implementing st/ld
primitives which will use this function).
As well, remove reference to TARGET_BIG_ENDIAN, as we are about to
remove this dependency.
Where is the TARGET_BIG_ENDIAN reference being remove
Signed-off-by: Pierrick Bouvier
---
system/ioport.c| 1 -
system/meson.build | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/system/ioport.c b/system/ioport.c
index 55c2a752396..89daae9d602 100644
--- a/system/ioport.c
+++ b/system/ioport.c
@@ -26,7 +26,6 @@
*/
#inc
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/tswap.h | 11 ++-
cpu-target.c | 1 +
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/include/exec/tswap.h b/include/exec/tswap.h
index ecd4faef015..2683da0adb7 100644
--- a/include/ex
On Thu, 6 Mar 2025 02:33:37 +
Alireza Sanaee via wrote:
Hi everyone,
v1 -> v2: I just rebased this patchset which initially was posted in
Sep 2024.
Thanks,
Alireza
> OS like Linux is using PPTT processor node's identical implementation
> flag [1] to infer whether the whole system or a cert
On 10.03.2025 10:23, Cédric Le Goater wrote:
On 3/10/25 09:17, Avihai Horon wrote:
On 07/03/2025 12:57, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
Wire data commonly use BE byte order (including in the existing migration
On Tue, Mar 11, 2025 at 03:33:23PM +, Daniel P. Berrangé wrote:
> On Tue, Mar 11, 2025 at 11:20:50AM -0400, Peter Xu wrote:
> > On Tue, Mar 11, 2025 at 08:13:16AM +, Daniel P. Berrangé wrote:
> > > On Mon, Mar 10, 2025 at 04:03:26PM -0400, Peter Xu wrote:
> > > > On Mon, Mar 10, 2025 at 07:
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