Hello everyone,
This patch adds support for the system timer interrupts
in QEMU's BCM2838 model. It defines a new constant
called GIC400_TIMER_INT, and connects 4 timer interupts
to the GIC-400.
Previously timer interupts were not being routed to the
interupt controller, causing scheduling, and s
Eliminate code repetition by using the appropriate helpers.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 65 +--
1 file changed, 8 insertions(+), 57 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index cfea
Two minor patches extracted from a larger set.
r~
Richard Henderson (2):
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
tcg/loongarch64/tcg-target-has.h | 2 -
tcg/riscv/tcg-target-has.h | 2 -
tcg/i386/t
These defines never should have been added as they were
never used. Only 32-bit hosts may have these opcodes and
they have them unconditionally.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-has.h | 2 --
tcg/riscv/tcg-target-has.h | 2 --
2 files changed, 4 deletions(-)
On 2/16/25 12:41, Richard Henderson wrote:
I don't think this is a good change to make.
fixing varargs codegen in GCC/Clang would be a good change. count
based varargs can be reasoned about statically relatively easily. what
is it like with an explicit inline as opposed to just static?
Inli
From: Mikael Szreder
The gdbstub implementation for the Sparc architecture would
incorrectly calculate the the floating point register offset.
This resulted in, for example, registers f32 and f34 to point to
the same value.
The issue was caused by the confusion between even register numbers
and
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 15 ++---
tcg/loongarch64/tcg-target-con-str.h | 1 -
tcg/loongarch64/tcg-target.c.inc | 32
3
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target-con-set.h | 10 +-
tcg/riscv/tcg-target-con-str.h | 1 -
tcg/riscv/tcg-target.c.inc | 28
3 files changed, 17 ins
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg-op-ldst.c | 21 +++--
tcg/tcg.c | 4 +---
2 files changed, 4 insertions(+), 21 deletions(-)
diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c
index 77271e0193..7ba9a3ef7e 100644
--- a/tcg/
Since we no longer support 64-bit guests on 32-bit hosts,
we can use a 32-bit type on a 32-bit host. This shrinks
the size of the structure to 16 bytes on a 32-bit host.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/tlb-common.h | 10 +-
accel/tc
For loongarch, mips, riscv and sparc, a zero register is
available all the time. For aarch64, register index 31
depends on context: sometimes it is the stack pointer,
and sometimes it is the zero register.
Introduce a new general-purpose constraint which maps 0
to TCG_REG_ZERO, if defined. This
From: Artyom Tarasenko
Fake access to
PCR Performance Control Register
and
PIC Performance Instrumentation Counter.
Ignore writes in privileged mode, and return 0 on reads.
This allows booting Tribblix, MilaX and v9os under Niagara target.
Signed-off-by: Artyom Tarasenko
Reviewed-by: Ri
Since 64-on-32 is now unsupported, guest addresses always
fit in one host register. Drop the replication of opcodes.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 28 ++--
tcg/optimize.c | 21 ++
tcg/tcg-op-ldst.c| 82 +-
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target-con-set.h | 12 ++--
tcg/sparc64/tcg-target-con-str.h | 1 -
tcg/sparc64/tcg-target.c.inc | 17 +++--
3 files changed, 13 insert
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target-con-set.h | 26 ++---
tcg/mips/tcg-target-con-str.h | 1 -
tcg/mips/tcg-target.c.inc | 44 ++-
3 files
This is now prohibited in configuration.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/qemu/atomic.h | 18 +++--
include/tcg/oversized-guest.h | 23 --
accel/tcg/cputlb.c | 7 ---
accel/tcg/tcg-all.c
Note that 'Z' is still used for addsub2.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-con-set.h | 12 -
tcg/aarch64/tcg-target.c.inc | 46 ++--
2 files changed, 26 insertions(+), 32 deletions(-)
diff --git a/tcg/aarch64/tcg-target-con-set.h
The guest address will now always fit in one register.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 75
1 file changed, 23 insertions(+), 52 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/
The guest address will now always fit in one register.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 62 ++-
1 file changed, 22 insertions(+), 40 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg
ble in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215
for you to fetch changes up to 2132751069134114814c7e1609e9cf644f077aad:
target/sparc: fake UltraSPARC T1 PCR and PIC registers (2025-02-15 12:04
There is now always only one guest address register.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 18 +-
tcg/aarch64/tcg-target.c.inc | 4 ++--
tcg/arm/tcg-target.c.inc | 4 ++--
tcg/i386/tcg-target.c.i
Since we no longer support 64-bit guests on 32-bit hosts,
we can use a 32-bit type on a 32-bit host.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/vaddr.h | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/include/exec/va
The guest address will now always fit in one register.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 56 ++-
1 file changed, 20 insertions(+), 36 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg
From: Fabiano Rosas
When complying with the alignment requested in the ELF and unmapping
the excess reservation, having align_end not aligned to the guest page
causes the unmap to be rejected by the alignment check at
target_munmap and later brk adjustments hit an EEXIST.
Fix by aligning the sta
From: Andreas Schwab
SA_RESTORER and the associated sa_restorer field of struct sigaction are
an obsolete feature, not expected to be used by future architectures.
They are also absent on RISC-V, LoongArch, Hexagon and OpenRISC, but
defined due to their use of generic/signal.h. This leads to cor
The declaration uses uint64_t for addr.
Fixes: 595cd9ce2ec ("plugins: add plugin API to read guest memory")
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
plugins/api.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/plugins/api.c b/plugins/api.c
in
The declarations use vaddr for size.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 17e2251695..75d075d044 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1
From: Mikael Szreder
A bug was introduced in commit 0bba7572d40d which causes the fdtox
and fqtox instructions to incorrectly select the destination registers.
More information and a test program can be found in issue #2802.
Fixes: 0bba7572d40d ("target/sparc: Perform DFPREG/QFPREG in decodetree
These should have been removed with the rest. There are
a couple of hosts which can emit guest_base into the
constant pool: aarch64, mips64, ppc64, riscv64.
Fixes: a417ef835058 ("tcg: Remove TCG_TARGET_NEED_LDST_LABELS and
TCG_TARGET_NEED_POOL_LABELS")
Signed-off-by: Richard Henderson
---
tcg/
The guest address will now always be TCG_TYPE_I32.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 63 ++--
1 file changed, 21 insertions(+), 42 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 05bb367a39..25
On 2/15/25 14:40, Michael Clark wrote:
On 2/16/25 10:50, Richard Henderson wrote:
On 2/15/25 12:24, Michael Clark wrote:
Why? varargs generally produces horrible code.
The split between alloc and insert was intentional to avoid this.
it's pretty good code on SysV because it goes via register
On 2/16/25 09:24, Michael Clark wrote:
I actually have a VM in mind that has a constant stream with it's own
counter that branches called IB (immediate base). IB is set in call
procedure and we pack a vector into the link register with the relative
offset of the program counter and immediate ba
On 2/16/25 10:50, Richard Henderson wrote:
On 2/15/25 12:24, Michael Clark wrote:
Why? varargs generally produces horrible code.
The split between alloc and insert was intentional to avoid this.
it's pretty good code on SysV because it goes via registers except for
perhaps new_pool_l8 which
On 2/15/25 12:24, Michael Clark wrote:
Why? varargs generally produces horrible code.
The split between alloc and insert was intentional to avoid this.
it's pretty good code on SysV because it goes via registers except for perhaps new_pool_l8
which will spill to stack and get copied unless th
On 2/16/25 06:58, Richard Henderson wrote:
On 2/14/25 18:11, Michael Clark wrote:
the intent of this patch is more conventional nomenclature
but the constant pool data code is also simplified a little.
- merge new_pool_{alloc,insert} -> new_pool_data.
- rename TCGLabelPoolData -> TCGData.
- ren
On 2/11/25 19:46, Richard Henderson wrote:
Based-on:20250205040341.2056361-1-richard.hender...@linaro.org
("[PATCH 00/11] tcg: Cleanups after disallowing 64-on-32")
Introduce a new general-purpose constraint which maps 0
to TCG_REG_ZERO, if defined. This differs from existing
constant constrain
On 2/4/25 20:03, Richard Henderson wrote:
This is not complete by any means, but it's a start.
r~
Based-on: 20250204215359.1238808-1-richard.hender...@linaro.org
("[PATCH v3 00/12] meson: Deprecate 32-bit host support")
Richard Henderson (11):
tcg: Drop support for two address registers
On 2/9/25 13:12, Artyom Tarasenko wrote:
fake access to
PCR Performance Control Register
and
PIC Performance Instrumentation Counter.
Ignore writes in privileged mode, and return 0 on reads.
This allows booting Tribblix, MilaX and v9os under Niagara target.
Signed-off-by: Artyom Tarasenko
---
On 2/13/25 23:03, Mikael Szreder wrote:
The gdbstub implementation for the Sparc architecture would
incorrectly calculate the the floating point register offset.
This resulted in, for example, registers f32 and f34 to point to
the same value.
The issue was caused by the confusion between even re
On 2/5/25 01:03, Mikael Szreder wrote:
Changelog:
v2:
- Corrected a mistake I made in the FqTOx instruction
- Fixed issues in the FsTOx, FxTOs, FxTOd, FxTOq instructions as well
Queued, squashing the two patches together.
r~
On 2/10/25 04:59, Andreas Schwab wrote:
SA_RESTORER and the associated sa_restorer field of struct sigaction are
an obsolete feature, not expected to be used by future architectures.
They are also absent on RISC-V, LoongArch, Hexagon and OpenRISC, but
defined due to their use of generic/signal.h.
On 2/15/25 11:06, Richard Henderson wrote:
On 2/13/25 06:35, Fabiano Rosas wrote:
When complying with the alignment requested in the ELF and unmapping
the excess reservation, having align_end not aligned to the guest page
causes the unmap to be rejected by the alignment check at
target_munmap an
On 2/13/25 06:35, Fabiano Rosas wrote:
When complying with the alignment requested in the ELF and unmapping
the excess reservation, having align_end not aligned to the guest page
causes the unmap to be rejected by the alignment check at
target_munmap and later brk adjustments hit an EEXIST.
Fix
On 2/15/25 09:09, Richard Henderson wrote:
On 2/15/25 01:21, Keith Packard via wrote:
Functions which modify virtual machine state (such as virtual
registers stored in memory) must not be marked TCG_CALL_NO_WG as that
tells the optimizer that virtual registers values already loaded in
machine
On 2/14/25 18:16, Keith Packard via wrote:
The ROM images all get deleted as they've been loaded to memory, so we
can't go fetch the reset vector from there. Instead, fetch it from
memory. To make that work, we need to execute the delayed mmu setup
function tcg_commit_cpu as that wires up memory
On 2/14/25 18:16, Keith Packard via wrote:
The documentation says the vector is at 0xff80, instead of the
previous value of 0xffc0. That value must have been a bug because
the standard vector values (20, 21, 23, 25, 30) were all
past the end of the array.
Signed-off-by: Keith Packard
--
On 2/14/25 18:16, Keith Packard via wrote:
Users can use -device loader to get an ELF file loaded to
memory, so we don't need to require one of these options.
Signed-off-by: Keith Packard
---
hw/rx/rx-gdbsim.c | 3 ---
1 file changed, 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 2/14/25 18:11, Michael Clark wrote:
the intent of this patch is more conventional nomenclature
but the constant pool data code is also simplified a little.
- merge new_pool_{alloc,insert} -> new_pool_data.
- rename TCGLabelPoolData -> TCGData.
- rename pool_labels -> pool_data.
- rename macro
13.02.2025 19:00, Paolo Bonzini wrote:
From: Volker Rümelin
Windows only:
The libSDL2 Windows message loop needs the libSDL2 Windows low
level keyboard hook procedure to grab the left and right Windows
keys correctly. Reenable the SDL2 Windows keyboard hook procedure.
Since SDL2 2.30.4 the SD
On 2/15/25 01:21, Keith Packard via wrote:
Functions which modify virtual machine state (such as virtual
registers stored in memory) must not be marked TCG_CALL_NO_WG as that
tells the optimizer that virtual registers values already loaded in
machine registers are still valid, hence discards an
Hello,
I have implemented support for PCI MSI capability CANbus card support; fully
tested using QNX operating system guest image. How can I go about contributing
this to the main repo:
https://github.com/Deniz-Eren/qemu/blob/feature/can-sja100-pci-msi-support/hw/net/can/can_pcm26d2ca_pci.c
From: Prasad Pandit
Hello,
* This series (v6) shuts down Multifd threads before starting Postcopy
migration. It helps to avoid an issue of multifd pages arriving late
at the destination during Postcopy phase and corrupting the vCPU
state. It also reorders the qtest patches and does some re
From: Prasad Pandit
Move MULTIFD_ macros to the header file so that
they are accessible from other source files.
Reviewed-by: Fabiano Rosas
Signed-off-by: Prasad Pandit
---
migration/multifd.c | 5 -
migration/multifd.h | 5 +
2 files changed, 5 insertions(+), 5 deletions(-)
v5: no c
From: Prasad Pandit
Migration capabilities are set in multiple '.start_hook'
functions for various tests. Instead, consolidate setting
capabilities in 'set_migration_capabilities()' function
which is called from various 'test_*_common()' functions.
While simplifying the capabilities setting, it h
From: Prasad Pandit
Enable Multifd and Postcopy migration together.
The migration_ioc_process_incoming() routine
checks magic value sent on each channel and
helps to properly setup multifd and postcopy
channels.
The Precopy and Multifd threads work during the
initial guest RAM transfer. When mig
From: Prasad Pandit
Add new qtests to run postcopy migration with multifd
channels enabled.
Signed-off-by: Prasad Pandit
---
tests/qtest/migration/compression-tests.c | 13
tests/qtest/migration/framework.c | 4 +++
tests/qtest/migration/postcopy-tests.c| 23 +
On Fri, Feb 14, 2025 at 9:26 PM Alexander Graf wrote:
>
>
> On 14.02.25 16:35, Ani Sinha wrote:
> > On Mon, Feb 3, 2025 at 3:50 AM Alexander Graf wrote:
> >> Hey Ani!
> >>
> >> On 28.01.25 22:31, Ani Sinha wrote:
>
>
> [...]
>
>
> >>> diff --git a/hw/core/machine.c b/hw/core/machine.c
> >>> index
> Functions which modify virtual machine state (such as virtual
> registers stored in memory) must not be marked TCG_CALL_NO_WG as that
> tells the optimizer that virtual registers values already loaded in
> machine registers are still valid, hence discards any changes which
> these helpers may ha
On Fri, Feb 14, 2025 at 9:02 PM Konstantin Shkolnyy wrote:
>
> On 2/13/2025 20:24, Lei Yang wrote:
> > I tested this patch with vdpa's regression tests, everything works fine.
> >
> > Tested-by: Lei Yang
>
> Could you point me to those tests?
Sure, the test scenarios include ping, mq tests under
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