On 2/16/25 09:24, Michael Clark wrote:
I actually have a VM in mind that has a constant stream with it's own
counter that branches called IB (immediate base). IB is set in call
procedure and we pack a vector into the link register with the relative
offset of the program counter and immediate base register (i32,i32)
gives call ±2GiB reach. link register no longer has absolute address.
and there is a branch instruction for the constant stream. return needs
two immediate offsets displaced from the text and constant entry points
to compute the return address.
btw here this is the instruction packet I have in mind for a CPU with
immediate blocks. it has much simpler length decoding than RISC-V and
less instruction forms too. two regslots can be bonded for a larger
indirect immediate slot using a constant from the current constant block
in the constant stream relative to PC/IB. 64-bit instructions can have 6
inputs/outputs which I have packed for vector in a sketch and it works.
it doesn't have 48-bit instructions because we simplified length
decoding compared to RISC-V. and decoding can be more easily vectorized
than RISC-V but we lost 1 bit in the 16-bit packet due to that. and I
have a python model that synthesizes logic for parallel decoders
https://anarch128.org/~mclark/VLI.pdf
I'm filling out the 16-bit opcode space. I need to add a constant with a
(i32,i32) relative immediate to ret to adjust for relative link register
so the return also needs a constant from the constant block aswell. it's
symmetrical but I don't have a software model yet.
https://gist.github.com/michaeljclark/8f9b81e5e40488035dc252c9da3ecc2e
in two to three years I may have a POC translator. I'm still working on
codegen for a new X86 backend. for VLI, 16-wide or 8 x 32-bit packets
(256-bits) is plausible with vastly simpler decode logic than X86.
that's like a 16/32/64-bit RISC front-end. at the moment I am thinking
of allowing 16-bit alignment for larger instruction words but I haven't
tried to synthesize a decoder yet. but I think much simpler than RISC-V
because 2 wires per packet for length vs up-to 7.
