Hello everyone,
This patch adds support for the system timer interrupts
in QEMU's BCM2838 model. It defines a new constant
called GIC400_TIMER_INT, and connects 4 timer interupts
to the GIC-400.
Previously timer interupts were not being routed to the
interupt controller, causing scheduling, and some other
stuff to have issues (me and a few friends bumped into
this, and that's why this was written lol).
Signed-off-by: Sourojeet Adhikari <s23ad...@csclub.uwaterloo.ca>
---
hw/arm/bcm2838.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/hw/arm/bcm2838.c b/hw/arm/bcm2838.c
index ddb7c5f..0a4179f 100644
--- a/hw/arm/bcm2838.c
+++ b/hw/arm/bcm2838.c
@@ -21,6 +21,8 @@
#define GIC400_TIMER_S_EL1_IRQ 13
#define GIC400_TIMER_NS_EL1_IRQ 14
#define GIC400_LEGACY_IRQ 15
+#define GIC400_TIMER_INT (96 - 32)
+
/* Number of external interrupt lines to configure the GIC with */
#define GIC_NUM_IRQS 192
@@ -176,6 +178,15 @@ static void bcm2838_realize(DeviceState *dev, Error
**errp)
qdev_get_gpio_in(gicdev, PPI(n, VIRTUAL_PMU_IRQ)));
}
+ sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->systmr), 0,
+ qdev_get_gpio_in(DEVICE(&s->gic), GIC400_TIMER_INT +
INTERRUPT_TIMER0));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->systmr), 1,
+ qdev_get_gpio_in(DEVICE(&s->gic), GIC400_TIMER_INT +
INTERRUPT_TIMER1));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->systmr), 2,
+ qdev_get_gpio_in(DEVICE(&s->gic), GIC400_TIMER_INT +
INTERRUPT_TIMER2));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->systmr), 3,
+ qdev_get_gpio_in(DEVICE(&s->gic), GIC400_TIMER_INT +
INTERRUPT_TIMER3));
+
/* Connect UART0 to the interrupt controller */
sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->uart0), 0,
qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_UART0));
--
2.48.1
