On Thu, 2025-02-06 at 14:26 -0700, Alex Williamson wrote:
> On Thu, 6 Feb 2025 13:13:39 +0100
> Corvin Köhne wrote:
>
> > From: Corvin Köhne
> >
> > We've recently imported the PCI ID list of knwon Intel GPU devices from
> > Linux. It allows us to properly match GPUs to their generation withou
The following patches are queued for QEMU stable v7.2.16:
https://gitlab.com/qemu-project/qemu/-/commits/staging-7.2
Patch freeze is 2025-02-06 (frozen), and the release is planned for 2025-02-08:
https://wiki.qemu.org/Planning/7.2
Please respond here or CC qemu-sta...@nongnu.org on any pat
From: Hongren Zheng
When USBPacket in OUT direction has larger payload
than the ep_out_buffer (of size 512), a buffer overflow
would occur.
It could be fixed by limiting the size of usb_packet_copy
to be at most buffer size. Further optimization gets rid
of the ep_out_buffer and directly uses ep
From: Peter Maydell
The pseudocode ResetSVEState() does:
FPSR = ZeroExtend(0x089f<31:0>, 64);
but QEMU's arm_reset_sve_state() called vfp_set_fpcr() by accident.
Before the advent of FEAT_AFP, this was only setting a collection of
RES0 bits, which vfp_set_fpsr() would then ignore, so the
On 2025/02/06 22:23, BALATON Zoltan wrote:
On Thu, 6 Feb 2025, Akihiko Odaki wrote:
On 2025/02/06 18:48, Markus Armbruster wrote:
This problem can be solved
using an existing mechanism, OnOffAuto, which differentiates the "auto"
state and explicit th
object_property_help() uses the conventional command line syntax instead
of the JSON syntax. In particular,
- Key-value pairs are written in the command line syntax.
- bool description passed to the function says on/off instead of
true/false.
However, there is one exception: default values are f
Hi all,
Accidentally added v2 tag. Please ignore it, this is version 1.
On 2/7/2025 10:23 AM, Sairaj Kodilkar wrote:
This series provides few bug fixes for emulated AMD IOMMU. The series is based
on top of qemu upstream master commit d922088eb4ba.
Patch 1: The code was using wrong DTE field to
This series provides few bug fixes for emulated AMD IOMMU. The series is based
on top of qemu upstream master commit d922088eb4ba.
Patch 1: The code was using wrong DTE field to determine interrupt passthrough.
Hence replaced it with correct field according to [1].
Patch 2: Current code
AMD IOMMU provides the base address of control registers through
IVRS table and PCI capability. Since this base address is of 64 bit,
use 32 bits mask (instead of 16 bits) to set BAR low and high.
Fixes: d29a09ca68 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Sairaj Kodilkar
Reviewed-by: Vasan
Interrupt passthrough is determine by the bits 191,190,187-184.
These bits are part of the 3rd quad word (i.e. index 2) in DTE. Hence
replace dte[3] by dte[2].
Fixes: b44159fe0 ("x86_iommu/amd: Add interrupt remap support when VAPIC is not
enabled")
Signed-off-by: Sairaj Kodilkar
Reviewed-by: Va
On Fri, Jan 31, 2025 at 8:18 AM Markus Armbruster wrote:
> Cc: John Snow for Python typing expertise.
>
> Daniel P. Berrangé writes:
>
> > This replaces use of the constants from the QapiSpecialFeatures
> > enum, with constants from the auto-generate QapiFeatures enum
> > in qapi-features.h
> >
On Tue, 4 Feb 2025 at 22:37, Peter Maydell wrote:
> On Thu, 30 Jan 2025 at 22:31, Edgar E. Iglesias
> wrote:
> > On Mon, Jan 27, 2025 at 8:40 AM Peter Maydell
> > wrote:
> >> On Thu, 19 Dec 2024 at 06:17, Andrew.Yuan
> >> wrote:
> >> > -rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr
On Tue, 4 Feb 2025 at 08:37, Peter Maydell wrote:
> On Thu, 30 Jan 2025 at 22:31, Edgar E. Iglesias
> wrote:
> > On Mon, Jan 27, 2025 at 8:40 AM Peter Maydell
> wrote:
> >> On Thu, 19 Dec 2024 at 06:17, Andrew.Yuan
> wrote:
> >> > -rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset
On Thu, 6 Feb 2025, Bernhard Beschow wrote:
Am 2. Februar 2025 01:25:22 UTC schrieb BALATON Zoltan :
On Sat, 1 Feb 2025, Bernhard Beschow wrote:
Am 1. Februar 2025 14:55:15 UTC schrieb Bernhard Beschow :
Am 30. Januar 2025 12:45:58 UTC schrieb BALATON Zoltan :
On Wed, 15 Jan 2025, BALATON Zol
On Thu, Feb 06, 2025 at 02:46:42PM -0800, Nicolin Chen wrote:
> > You'd use the command line information and wouldn't need GET_HW_INFO,
> > it would be complicated
>
> Do you mean the "-device arm-smmuv3-accel,id=xx" line? This still
> won't give us the host IDR/IIDR register values to probe a vSM
Am 2. Februar 2025 01:25:22 UTC schrieb BALATON Zoltan :
>On Sat, 1 Feb 2025, Bernhard Beschow wrote:
>> Am 1. Februar 2025 14:55:15 UTC schrieb Bernhard Beschow :
>>> Am 30. Januar 2025 12:45:58 UTC schrieb BALATON Zoltan :
On Wed, 15 Jan 2025, BALATON Zoltan wrote:
> This allows guest
On Wed, Feb 05, 2025 at 05:57:10PM +0530, Prasad Pandit wrote:
> From: Prasad Pandit
>
> Enable Multifd and Postcopy migration together.
> The migration_ioc_process_incoming() routine
> checks magic value sent on each channel and
> helps to properly setup multifd and postcopy
> channels.
>
> The
From: Dongwon Kim
This partially reverts commit 77bf310084dad38b3a2badf01766c659056f1cf2
which causes some guest display corruption when gtk-gl-area
is used for GTK rendering (e.g. Wayland Compositor) possibly due to
simulataneous accesses on the guest frame buffer by host compositor
and the gues
On Thu, Feb 06, 2025 at 05:11:13PM -0400, Jason Gunthorpe wrote:
> On Thu, Feb 06, 2025 at 12:48:40PM -0800, Nicolin Chen wrote:
> > On Thu, Feb 06, 2025 at 04:38:55PM -0400, Jason Gunthorpe wrote:
> > > On Thu, Feb 06, 2025 at 12:33:19PM -0800, Nicolin Chen wrote:
> > > > On Thu, Feb 06, 2025 at 0
On Wed, Feb 05, 2025 at 05:57:12PM +0530, Prasad Pandit wrote:
> From: Prasad Pandit
>
> Migration capabilities are set in multiple '.start_hook'
> functions for various tests. Instead, consolidate setting
> capabilities in 'set_migration_capabilities()' function
> which is called from various 't
On Wed, Feb 05, 2025 at 05:57:09PM +0530, Prasad Pandit wrote:
> From: Prasad Pandit
>
> Refactor ram_save_target_page legacy and multifd
> functions into one. Other than simplifying it,
> it frees 'migration_ops' object from usage, so it
> is expunged.
>
> Reviewed-by: Fabiano Rosas
> Signed-o
On Wed, Feb 05, 2025 at 05:57:08PM +0530, Prasad Pandit wrote:
> From: Prasad Pandit
>
> Move MULTIFD_ macros to the header file so that
> they are accessible from other source files.
>
> Reviewed-by: Fabiano Rosas
> Signed-off-by: Prasad Pandit
Reviewed-by: Peter Xu
--
Peter Xu
Il gio 6 feb 2025, 11:42 Zhao Liu ha scritto:
> > diff --git a/rust/hw/char/pl011/src/device_class.rs
> b/rust/hw/char/pl011/src/device_class.rs
> > index 8a157a663fb..dbef93f6cb3 100644
> > --- a/rust/hw/char/pl011/src/device_class.rs
> > +++ b/rust/hw/char/pl011/src/device_class.rs
> > @@ -12,7
NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR
module. Since we don't simulate a detailed memory controller, we
need to store this information directly similar to the NPCM7XX's
INCTR3 register.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c
Changes since v3:
1. Removed REGS_END constants according to code review.
2. Added a few asserts according to code review.
3. A few minor style changes.
Changes since v2:
1. Update doc to include npcm845-evb description
2. Add g_assert for register size in CLK and GCR enter_reset function
3. Fix
A lot of NPCM7XX and NPCM8XX GCR modules share the same code,
this commit moves the NPCM7XX GCR to NPCM GCR for these
properties.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 92 +-
hw/misc/trace-events | 6 +--
inc
The NPCM8xx GCR device can be accessed with 64-bit memory operations.
This patch supports that.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 94 +---
hw/misc/trace-events | 4 +-
2 files changed, 74 insertions(+), 24 deleti
On Thu, Feb 06, 2025 at 12:41:50PM +0100, Maciej S. Szmigiero wrote:
> On 5.02.2025 16:55, Peter Xu wrote:
> > On Wed, Feb 05, 2025 at 12:53:21PM +0100, Maciej S. Szmigiero wrote:
> > > On 4.02.2025 21:34, Peter Xu wrote:
> > > > On Tue, Feb 04, 2025 at 08:32:15PM +0100, Maciej S. Szmigiero wrote:
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
This document describes the NPCM8XX SoC and an evaluation board
(NPCM 845 EVB).
Signed-off-by: Hao Wu
---
docs/system/arm/nuvoton.rst | 27
These 2 values are different between NPCM7XX and NPCM8XX
GCRs. So we add them to the class and assign different values
to them.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 27 ---
include/hw/misc/npcm_gcr.h | 13 +++--
2 file
These 2 values are different between NPCM7XX and NPCM8XX
CLKs. So we add them to the class and assign different values
to them.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 18 --
hw/misc/npcm_gcr.c | 2 ++
include/hw/misc/npcm_clk.h
Signed-off-by: Hao Wu
---
configs/devices/aarch64-softmmu/default.mak | 1 +
hw/arm/Kconfig | 13 +
hw/arm/meson.build | 1 +
hw/arm/npcm8xx.c| 804
include/hw/arm/npcm8xx.h
NPCM8XX adds a few new registers and have a different set of reset
values to the CLK modules. This patch supports them.
This patch doesn't support the new clock values generated by these
registers. Currently no modules use these new clock values so they
are not necessary at this point.
Implementat
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 129 -
include/hw/misc/npcm_gcr.h | 6 +-
2 files changed, 132 insertions(+), 3 deletions(-)
diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c
index d89e8c2c3b..fe6e332de7
The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
PHY. This implementation contains all the default registers and
the soft reset feature that are required to load the Linux kernel
driver. Further features have not been implemented yet.
Signed-off-by: Hao Wu
Reviewed-by: Peter May
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/arm/meson.build | 2 +-
hw/arm/npcm8xx_boards.c | 253 +++
include/hw/arm/npcm8xx.h | 21
3 files changed, 275 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/npcm8xx_boards.c
diff
This allows different FIUs to have different flash sizes, useful
in NPCM8XX which has multiple different sized FIU modules.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 6 ++
hw/ssi/npcm7xx_fiu.c | 16 ++--
include/hw/ssi/npcm7xx_f
A lot of NPCM7XX and NPCM8XX CLK modules share the same code,
this commit moves the NPCM7XX CLK to NPCM CLK for these
properties.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 106 +
hw/misc/trace-events | 6 +--
in
NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module
needs to fit both. This commit changes the name of the GCR module.
Future commits will add the support for NPCM8XX GCRs.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/meson.build | 2 +-
The bootrom is a minimal bootrom used to load an NPCM8XX image.
The source code is located in the same repo as the NPCM7XX one:
github.com/google/vbootrom/tree/master/npcm8xx.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
MAINTAINERS | 1 +
pc-bios/README |
NPCM7XX and NPCM8XX have a different set of CLK registers. This
commit changes the name of the clk files to be used by both
NPCM7XX and NPCM8XX CLK modules.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/meson.build | 2 +-
hw/misc/{npcm7xx_clk.c => npcm_
This newer vbootrom supports NPCM8xx. Similar to the NPCM7XX one
it supports loading the UBoot from the SPI device and not more.
We updated the npcm7xx bootrom to be compiled from this version.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
pc-bios/npcm7xx_bootrom.bin | Bin 768 -> 768 by
Am 6. Februar 2025 17:32:31 UTC schrieb Peter Maydell
:
>On Tue, 4 Feb 2025 at 09:21, Bernhard Beschow wrote:
>>
>> The implementation just allows Linux to determine date and time.
>>
>> Signed-off-by: Bernhard Beschow
>> ---
>> MAINTAINERS | 1 +
>> hw/rtc/rs5c372.c| 227 +
On Tue, Feb 04, 2025 at 07:25:12PM +0100, Maciej S. Szmigiero wrote:
> That's for the multifd channel recv thread main loop only, if @Peter
> wants to patch also the mid-stream page receive methods and the main
> migration channel receive then qio_channel_read(), qio_channel_read_all(),
> qio_chann
On Thu, Feb 06, 2025 at 02:32:12PM -0300, Fabiano Rosas wrote:
> > In any case we'd still need some kind of a compatibility behavior for
> > the TLS bit stream emitted by older QEMU versions (which is always
> > improperly terminated).
> >
>
> There is no compat issue. For <= 9.2, QEMU is still do
On 2/6/25 05:10, Philippe Mathieu-Daudé wrote:
Commit f0ec14c78c4 ("tests/avocado: Fix console data loss") fixed
QEMUMachine's problem with console, we don't need to use the sleep()
kludges.
Suggested-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
---
tests/functional/test_microblazeel_
On 2/6/25 05:10, Philippe Mathieu-Daudé wrote:
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness on the single machine usi
On Thu, 6 Feb 2025 13:13:39 +0100
Corvin Köhne wrote:
> From: Corvin Köhne
>
> We've recently imported the PCI ID list of knwon Intel GPU devices from
> Linux. It allows us to properly match GPUs to their generation without
> maintaining an own list of PCI IDs.
>
> Signed-off-by: Corvin Köhne
On 2/6/25 10:26, Paolo Bonzini wrote:
Start putting all the CPU definitions in a struct. Later this will replace
instance_init functions with declarative code, for now just remove the
ugly cast of class_data.
...
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ed9da692030..29cfae38b
On Thu, Feb 06, 2025 at 12:48:40PM -0800, Nicolin Chen wrote:
> On Thu, Feb 06, 2025 at 04:38:55PM -0400, Jason Gunthorpe wrote:
> > On Thu, Feb 06, 2025 at 12:33:19PM -0800, Nicolin Chen wrote:
> > > On Thu, Feb 06, 2025 at 02:22:01PM -0400, Jason Gunthorpe wrote:
> > > > On Thu, Feb 06, 2025 at 0
On 6.02.2025 18:58, Fabiano Rosas wrote:
Hi,
We've been discussing a way to stop multifd recv threads from getting
an error at the end of migration when the source threads close the
iochannel without ending the TLS session.
The original issue was introduced by commit 1d457daf86
("migration/mult
On 2/6/25 07:12, Peter Maydell wrote:
Currently if the user requests via -machine dumpdtb=file.dtb that we
dump the DTB, but the machine doesn't have a DTB, we silently ignore
the option. This is confusing to users, and is a legacy of the old
board-specific implementation of the option, where if
On 2/6/25 10:18, Philippe Mathieu-Daudé wrote:
opentitan_machine_init() calls get_system_memory(),
which is declared in "exec/address-spaces.h". Include
it in order to avoid when refactoring unrelated headers:
hw/riscv/opentitan.c:83:29: error: call to undeclared function
'get_system_memory'
On 2/6/25 10:18, Philippe Mathieu-Daudé wrote:
-M: Alistair Francis
+M: alistair.francis
Well this isn't right.
r~
On 2/6/25 07:12, Peter Maydell wrote:
Currently we handle the 'dumpdtb' machine sub-option ad-hoc in every
board model that has an FDT. It's up to the board code to make sure
it calls qemu_fdt_dumpdtb() in the right place.
This means we're inconsistent and often just ignore the user's
command l
On Thu, Feb 06, 2025 at 04:38:55PM -0400, Jason Gunthorpe wrote:
> On Thu, Feb 06, 2025 at 12:33:19PM -0800, Nicolin Chen wrote:
> > On Thu, Feb 06, 2025 at 02:22:01PM -0400, Jason Gunthorpe wrote:
> > > On Thu, Feb 06, 2025 at 06:18:14PM +, Shameerali Kolothum Thodi wrote:
> > >
> > > > > So
On 2/6/25 07:12, Peter Maydell wrote:
The openrisc machines don't setMachineState::fdt to point to their
DTB blob. This means that although the command line '-machine
dumpdtb=file.dtb' option works, the equivalent QMP and HMP monitor
commands do not, but instead produce the error "This machine d
On 2/6/25 07:12, Peter Maydell wrote:
In hmp_dumpdtb(), we print a message when the command succeeds. This
message is missing the trailing \n, so the HMP command prompt is
printed immediately after it. We also weren't capitalizing 'DTB', or
quoting the filename in the message. Fix these nits.
Am 06.02.2025 um 18:25 hat Philippe Mathieu-Daudé geschrieben:
> On 6/2/25 17:53, Kevin Wolf wrote:
> > Commit fc4e394b28 removed the last caller of blk_op_is_blocked(). Remove
> > the now unused function.
>
> fatal: ambiguous argument 'fc4e394b28': unknown revision or path not in the
> working tr
On Thu, Feb 06, 2025 at 12:33:19PM -0800, Nicolin Chen wrote:
> On Thu, Feb 06, 2025 at 02:22:01PM -0400, Jason Gunthorpe wrote:
> > On Thu, Feb 06, 2025 at 06:18:14PM +, Shameerali Kolothum Thodi wrote:
> >
> > > > So even if you invent an iommu ID we cannot accept it as a handle to
> > > > c
On Thu, Feb 06, 2025 at 02:22:01PM -0400, Jason Gunthorpe wrote:
> On Thu, Feb 06, 2025 at 06:18:14PM +, Shameerali Kolothum Thodi wrote:
>
> > > So even if you invent an iommu ID we cannot accept it as a handle to
> > > create viommu in iommufd.
> >
> > Creating the vIOMMU only happens when
Emphasize that these are 4-way dot products.
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 22 +++---
target/arm/tcg/translate-a64.c | 14 +++---
target/arm/tcg/translate-neon.c | 14 +++---
target/arm/tcg/translate-sve.c | 18 +-
On Thu, Feb 06, 2025 at 06:41:09PM +0800, Xu Yilun wrote:
> On Thu, Jan 30, 2025 at 11:28:11AM -0500, Peter Xu wrote:
> > On Sun, Jan 26, 2025 at 11:34:29AM +0800, Xu Yilun wrote:
> > > > Definitely not suggesting to install an invalid pointer anywhere. The
> > > > mapped pointer will still be val
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-sme.h| 18 +++
target/arm/tcg/sme_helper.c| 94 ++
target/arm/tcg/translate-sme.c | 29 +++
target/arm/tcg/sme.decode | 33
4 files changed, 174 insertions(+)
diff --g
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-sme.h| 12 ++
target/arm/tcg/sme_helper.c| 68 ++
target/arm/tcg/translate-sme.c | 35 +
target/arm/tcg/sme.decode | 11 ++
4 files changed, 126 insertions(+)
diff --gi
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 6 +++
target/arm/tcg/translate-sme.c | 85 ++
target/arm/tcg/vec_helper.c| 51
target/arm/tcg/sme.decode | 63 -
4 files changed, 204 inser
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-sme.h| 2 ++
target/arm/tcg/sme_helper.c| 38 ++
target/arm/tcg/translate-sme.c | 5 +
target/arm/tcg/sme.decode | 5 +
4 files changed, 50 insertions(+)
diff --git a/target/arm/tcg
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 9 +
target/arm/tcg/translate-sme.c | 14 ++
target/arm/tcg/vec_helper.c| 26 ++
target/arm/tcg/sme.decode | 18 ++
4 files changed, 67 insertions(+)
diff -
Inputs are a wider type of indeterminate sign.
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_internal.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h
index 205f85b8d3..ad6fef03e6 100644
--- a/target/arm/tcg/vec_
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-sme.h| 13
target/arm/tcg/sme_helper.c| 38 ++
target/arm/tcg/translate-sme.c | 16 ++
target/arm/tcg/sme.decode | 18
4 files changed, 85 insertions(+
Replace and remove do_sat_bhs.
This avoids multiple repetitions of INT*_MIN/MAX.
Signed-off-by: Richard Henderson
---
target/arm/tcg/sve_helper.c | 116 +++-
1 file changed, 48 insertions(+), 68 deletions(-)
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/t
Signed-off-by: Richard Henderson
---
tcg/tcg-op-gvec.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index d32a4f146d..1aad7b0864 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -483,8 +483,8 @@ static TCGType
To be used by both SVE2 and SME2.
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.h | 4
target/arm/tcg/gengvec64.c | 11 +++
target/arm/tcg/translate-sve.c | 8 +---
3 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/target/arm/tcg/translate
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-sme.h| 5 +++
target/arm/tcg/sme_helper.c| 74 ++
target/arm/tcg/translate-sme.c | 25
target/arm/tcg/sme.decode | 12 ++
4 files changed, 116 insertions(+)
diff --git a/targ
Signed-off-by: Richard Henderson
---
target/arm/tcg/cpu64.c| 7 ++-
docs/system/arm/emulation.rst | 3 +++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 29ab0ac79d..6fb821ad9a 100644
--- a/target/arm/tcg/cpu64.c
+++
Unify two copies of these inline functions.
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_internal.h | 21 +
target/arm/tcg/mve_helper.c | 21 -
target/arm/tcg/sve_helper.c | 21 -
3 files changed, 21 insertions(+), 42 del
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-sme.h| 18 +++
target/arm/tcg/sme_helper.c| 91 ++
target/arm/tcg/translate-sme.c | 35 +
target/arm/tcg/sme.decode | 22
4 files changed, 166 insertions(+)
diff --git
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-sme.h| 22 ++
target/arm/tcg/sme_helper.c| 60 +++
target/arm/tcg/translate-sme.c | 78 +++
target/arm/tcg/sme.decode | 135 +
4 files changed, 295 insertions
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sme.c | 95 ++
target/arm/tcg/sme.decode | 48 +
2 files changed, 143 insertions(+)
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index 9c0989baff..19
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sme.c | 9 +
target/arm/tcg/sme.decode | 9 +
2 files changed, 18 insertions(+)
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index a993870812..a4c683e12f 100644
--- a/target/arm/tcg
Signed-off-by: Richard Henderson
---
tcg/tcg-op-gvec.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 1aad7b0864..451091753d 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -534,9 +534,9 @@
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-sme.h| 15 +
target/arm/tcg/sme_helper.c| 52 +++
target/arm/tcg/translate-sme.c | 56 ++
target/arm/tcg/sme.decode | 17 +++
4 files changed, 140 in
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-sme.h| 3 +++
target/arm/tcg/sme_helper.c| 34 --
target/arm/tcg/translate-sme.c | 2 ++
target/arm/tcg/sme.decode | 2 ++
4 files changed, 31 insertions(+), 10 deletions(-)
diff --git a/ta
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-sme.h| 5
target/arm/tcg/sme_helper.c| 44 ++
target/arm/tcg/translate-sme.c | 18 ++
target/arm/tcg/sme.decode | 14 +++
4 files changed, 81 insertions(+)
diff --git
Decode tile number and index offset beforehand and separately.
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sme.c | 17 +
target/arm/tcg/sme.decode | 46 +++---
2 files changed, 38 insertions(+), 25 deletions(-)
diff --git a/target/a
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-sme.h| 11 +
target/arm/tcg/sme_helper.c| 42 ++
target/arm/tcg/translate-sme.c | 23 +++
target/arm/tcg/sme.decode | 11 +
4 files changed, 87 insertions(+)
di
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.h | 5 +
target/arm/tcg/translate-sme.c | 30 ++
target/arm/tcg/sme.decode | 12
3 files changed, 47 insertions(+)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/transla
Emphasize the non-fused nature of these multiply-add.
Matches other helpers such as gvec_rsqrts_nf_[hs].
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 8
target/arm/tcg/translate-neon.c | 4 ++--
target/arm/tcg/vec_helper.c | 8
3 files changed, 10
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sme.c | 5 +
target/arm/tcg/sme.decode | 5 +
2 files changed, 10 insertions(+)
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index 4b45459e77..a993870812 100644
--- a/target/arm/tcg/transla
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-sme.h| 12 +++
target/arm/tcg/sme_helper.c| 58 ++
target/arm/tcg/translate-sme.c | 37 ++
target/arm/tcg/sme.decode | 12 +++
4 files changed, 119 insertions(+)
di
The last use of this field was removed in b2fc7be972b9.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 61f959af8b..91edeae9ad 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -693,9 +693
The whole ZA state will also contain ZT0.
Make things easier in aarch64_set_svcr to zero both
by wrapping them in a common structure.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 48 +++---
linux-user/aarch64/signal.c| 4 +--
target/arm/c
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 2 ++
target/arm/tcg/translate-sme.c | 44 ++
target/arm/tcg/vec_helper.c| 2 ++
target/arm/tcg/sme.decode | 25 +++
4 files changed, 73 insertions(+)
diff --git a/tar
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sme.c | 17 +
target/arm/tcg/sme.decode | 9 +
2 files changed, 26 insertions(+)
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index 2885655cc5..c03daa535d 100644
--- a/targ
Prepare for more kinds of MOVA from SME2 by renaming the
existing SME1 MOVA to indicate tile to/from vector.
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sme.c | 12 +-
target/arm/tcg/sme.decode | 42 +-
2 files changed, 27 insertions
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sme.c | 65 ++
target/arm/tcg/sme.decode | 36 +++
2 files changed, 101 insertions(+)
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index 0e05153924..
Pipe the value through from SMCR_ELx through hflags
and into the disassembly context.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 ++
target/arm/tcg/translate.h | 1 +
target/arm/cpu.c | 3 +++
target/arm/tcg/hflags.c| 34 +
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sme.c | 31 +++
target/arm/tcg/sme.decode | 20
2 files changed, 51 insertions(+)
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index 09a4da1725..8aa
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sme.c | 25 +
target/arm/tcg/sme.decode | 9 +
2 files changed, 34 insertions(+)
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index e71e3ec8e3..78bd750701 100644
--
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 2 ++
target/arm/tcg/helper-sme.h| 2 ++
target/arm/tcg/sme_helper.c| 30 ++
target/arm/tcg/translate-sme.c | 16 ++
target/arm/tcg/vec_helper.c| 39
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