The current function used to generate GHES data is specific for
memory errors. Give a better name for it, as we now have a generic
function as well.
Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes-stub.c| 2 +-
hw/acpi/ghes.c
As described at: ACPI 6.5 spec at:
18.3.2. ACPI Error Source
In particular at GHES/GHESv2 table:
Table 18.10 Generic Hardware Error Source Structure
HEST source ID is actually a 16-bit value.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor M
On Tue, 3 Dec 2024 14:47:30 +0100
Mauro Carvalho Chehab wrote:
> Em Tue, 3 Dec 2024 12:51:43 +0100
> Igor Mammedov escreveu:
>
> > On Fri, 22 Nov 2024 10:11:30 +0100
> > Mauro Carvalho Chehab wrote:
> >
> > > Currently, CPER address location is calculated as an offset of
> > > the hardware_
Hi Philippe,
> Subject: Re: [PATCH v2 3/6] hw:sdhci: Introduce a new "capareg" class member
> to set the different Capability Registers.
>
> On 4/12/24 04:14, Jamin Lin wrote:
> > Hi Bernhard,
> >
> >> Subject: Re: [PATCH v2 3/6] hw:sdhci: Introduce a new "capareg" class
> >> member to set the di
Hi Philippe,
> Subject: Re: [PATCH v2 3/6] hw:sdhci: Introduce a new "capareg" class member
> to set the different Capability Registers.
>
> On 3/12/24 03:14, Jamin Lin via wrote:
> > Currently, it set the hardcode value of capability registers to all
> > ASPEED SOCs However, the value of capabil
Em Mon, 25 Nov 2024 11:56:43 +
Jonathan Cameron escreveu:
> On Fri, 22 Nov 2024 10:11:25 +0100
> Mauro Carvalho Chehab wrote:
>
> > Split the code into separate functions to allow using the
> > common CPER filling code by different error sources.
> >
> > The generic code was moved to ghes_
During the development of a patch series meant to allow GHESv2 error injections,
it was requested a change on how CPER offsets are calculated, by adding a new
BIOS pointer and reworking the GHES logic. See:
https://lore.kernel.org/qemu-devel/cover.1726293808.git.mchehab+hua...@kernel.org/
Such ch
GHES has two fields that are stored on HEST error source
blocks associated with notifications:
- notification type, which is a number defined at the ACPI spec
containing several arch-specific synchronous and assynchronous
types;
- source id, which is a HW/FW defined number, used to distinguish
Make error handling within ghes_record_cper_errors() consistent,
i.e. instead abort just print a error in case ghes GED is not found.
Reviewed-by: Jonathan Cameron
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
---
hw/acpi/ghes.c | 5 -
1 file changed, 4 insertions(+), 1 d
Reduce the ident of the function and prepares it for
the next changes.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
hw/acpi/ghes.c | 56 ++
1 file changed, 29 insertions
Now that we have also have a file to store HEST data location,
which is part of GHES, better name the file where CPER records
are stored.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
hw/acpi/ghes.c | 38 ++
This is just duplicating ACPI_GHES_ERROR_SOURCE_COUNT, which
has a better name. So, drop the duplication.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
hw/acpi/ghes.c | 7 ++-
include/hw/acpi/ghes.h | 3 ++-
2 files changed, 4 ins
Split the code into separate functions to allow using the
common CPER filling code by different error sources.
The generic code was moved to ghes_record_cper_errors(),
and ghes_gen_err_data_uncorrectable_recoverable() now contains
only a logic to fill the Generic Error Data part of the record,
as
Currently, CPER address location is calculated as an offset of
the hardware_errors table. It is also badly named, as the
offset actually used is the address where the CPER data starts,
and not the beginning of the error source.
Move the logic which calculates such offset to a separate
function, in
The hardware error firmware is where HEST error structures are
stored. Those can be GHESv2, but they can also be other types.
Better name the location of the hardware error.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
--
The 'physical_address' value is a faulty page. As such, 0 is
as valid as any other value.
Suggested-by: Igor Mammedov
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index edc74c38bf8a..a3dffd78b012 1
Align the header file with the actual implementation of
this function, as the first argument is source ID and not
notification type.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
Changes from v8:
- Non-rename/cleanup changes merged altogethe
Extending to multiple sources require a BIOS pointer to the
beginning of the HEST table, which in turn requires a backward-compatible
code.
So, the current code supports only one source. Ensure that and simplify
the code.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Review
We'll need this functionality in other functional tests, too, so
let's extract it into the qemu_test module.
Also add an __enter__ and __exit__ function that can be used for
using this functionality in a locked context, so that tests that
are running in parallel don't try to compete for the same p
This test matches exactly the first three lines of the following
test_no_vnc_change_password test, so there is exactly zero additional
test coverage in here.
Signed-off-by: Thomas Huth
---
tests/functional/test_vnc.py | 5 -
1 file changed, 5 deletions(-)
diff --git a/tests/functional/test_
Nothing thrilling in here, it's just a straight forward conversion.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
tests/functional/meson.build | 1 +
tests/{avocado/vnc.py => functional/test_vnc.py} | 12 +++-
Convert the vnc and migration test that use a find_free_ports()
function to look for a free port. Since the functional tests can
be run in parallel, we extract the find_free_ports() function
into a helper and provide a locking mechanism so that the tests
don't race for the free ports (see second pa
This file should belong to the R2D machine in the MAINTAINERS file.
Signed-off-by: Thomas Huth
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index aaf0505a21..727f18fae5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1643,7 +1643,7
When running "make -j$(nproc) check SPEED=thorough", the sh4_tuxrun
test is timing out for me, and using TIMEOUT_MULTIPLIER I can see
that it clearly takes more than 100 seconds to finish. Thus increase
the timeout setting of this test to avoid the problem.
Signed-off-by: Thomas Huth
---
tests/f
On 3/12/24 21:39, Richard Henderson wrote:
Remove "3" as a special case for which and simply
branch to return the desired value.
Signed-off-by: Richard Henderson
---
fpu/softfloat-parts.c.inc | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
Reviewed-by: Philippe
On 27/11/2024 10.37, Philippe Mathieu-Daudé wrote:
On 26/11/24 12:22, Philippe Mathieu-Daudé wrote:
We use PCIBus::flags to mask various flags. It is not
an enum, and doing so confuses static analyzers. Rename
the enum as singular. Use a generic unsigned type for
the mask.
Signed-off-by: Philip
On 26/11/2024 11.30, Cornelia Huck wrote:
Add 10.0 machine types for arm/i440fx/m68k/q35/s390x/spapr.
Signed-off-by: Cornelia Huck
---
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
hw/i386/pc.c | 3 +++
hw/i386/pc_piix.c | 13 ++
On 3/12/24 21:39, Richard Henderson wrote:
While all indices into val[] should be in [0-2], the mask
applied is two bits. To help static analysis see there is
no possibility of read beyond the end of the array, pad the
array to 4 entries, with the final being (implicitly) NULL.
Squash in previ
On 3/12/24 21:39, Richard Henderson wrote:
Assign the pointer return value to 'a' directly,
rather than going through an intermediary index.
Signed-off-by: Richard Henderson
---
fpu/softfloat-parts.c.inc | 32 ++--
1 file changed, 10 insertions(+), 22 deletions(-)
On 04/12/2024 04:34, Jason Wang wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> On Mon, Nov 11, 2024 at 4:39 PM Zhenzhong Duan
> wrote:
>>
>> Intel VT-d 3.0 introduces scalable mod
On 3/12/24 21:39, Richard Henderson wrote:
Now that float_status has a bunch of fp parameters,
it is easier to copy an existing structure than create
one from scratch. Begin by copying the structure that
corresponds to the FPSR and make only the adjustments
required for BFloat16 semantics.
Sign
On 3/12/24 21:39, Richard Henderson wrote:
Replace the "index" selecting between A and B with a result variable
of the proper type. This improves clarity within the function.
Signed-off-by: Richard Henderson
---
fpu/softfloat-parts.c.inc | 28 +---
1 file changed, 13
On 3/12/24 21:39, Richard Henderson wrote:
Inline pickNaN into its only caller. This makes one assert
redundant with the immediately preceding IF.
Signed-off-by: Richard Henderson
---
fpu/softfloat-parts.c.inc | 82 +
fpu/softfloat-specialize.c.inc | 96
On 3/12/24 21:39, Richard Henderson wrote:
Inline pickNaNMulAdd into its only caller. This makes
one assert redundant with the immediately preceding IF.
Signed-off-by: Richard Henderson
---
fpu/softfloat-parts.c.inc | 35 +-
fpu/softfloat-specialize.c.inc | 54 -
On 4/12/24 04:14, Jamin Lin wrote:
Hi Bernhard,
Subject: Re: [PATCH v2 3/6] hw:sdhci: Introduce a new "capareg" class member
to set the different Capability Registers.
Am 3. Dezember 2024 02:14:57 UTC schrieb Jamin Lin via
:
Currently, it set the hardcode value of capability registers to al
On Thu, Nov 14, 2024 at 2:19 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> 'sha' is defined in RVA22 as "augmented hypervisor extension" and
> consists of a set of named features that must be enabled.
>
> RVA23 makes 'sha' mandatory, so let's add official support for it in
> preparation to support
On Thu, Nov 14, 2024 at 2:19 AM Daniel Henrique Barboza
wrote:
>
> 'sha' is the augmented hypervisor extension, defined in RVA22 as a set of
> the following extensions:
>
> - RVH
> - Ssstateen
> - Shcounterenw (always present)
> - Shvstvala (always present)
> - Shtvala (always present)
> - Shvstve
On Thu, Nov 14, 2024 at 2:20 AM Daniel Henrique Barboza
wrote:
>
> shgatpa is defined in RVA22 as:
>
> "For each supported virtual memory scheme SvNN supported in satp, the
> corresponding hgatp SvNNx4 mode must be supported. The hgatp mode Bare
> must also be supported."
>
> Claim support for shg
On Thu, Nov 14, 2024 at 2:20 AM Daniel Henrique Barboza
wrote:
>
> shvsatpa is defined in RVA22 as:
>
> "All translation modes supported in satp must be supported in vsatp."
>
> This is always true in TCG so let's claim support for it.
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alis
On Thu, Nov 14, 2024 at 2:20 AM Daniel Henrique Barboza
wrote:
>
> shvstvecd is defined in RVA22 as:
>
> "vstvec.MODE must be capable of holding the value 0 (Direct).
> When vstvec.MODE=Direct, vstvec.BASE must be capable of holding any
> valid four-byte-aligned address."
>
> This is always true f
On Thu, Nov 14, 2024 at 2:20 AM Daniel Henrique Barboza
wrote:
>
> shtvala is described in RVA22 as:
>
> "htval must be written with the faulting guest physical address
> in all circumstances permitted by the ISA."
>
> This is the case since commit 3067553993, so claim support for shtvala.
>
> Sig
On Thu, Nov 14, 2024 at 2:20 AM Daniel Henrique Barboza
wrote:
>
> shvstvala is defined in RVA22 as:
>
> "vstval must be written in all cases described above for stval."
>
> By "cases describe above" the doc refer to the description of sstvala:
>
> "stval must be written with the faulting virtual
On Thu, Nov 14, 2024 at 2:20 AM Daniel Henrique Barboza
wrote:
>
> shcounterenw is defined in RVA22 as:
>
> "For any hpmcounter that is not read-only zero, the corresponding bit in
> hcounteren must be writable."
>
> This is always true in TCG so let's claim support for it.
>
> Signed-off-by: Dani
On Thu, Nov 14, 2024 at 2:20 AM Daniel Henrique Barboza
wrote:
>
> ssstateen is defined in RVA22 as:
>
> "Supervisor-mode view of the state-enable extension. The supervisor-mode
> (sstateen0-3) and hypervisor-mode (hstateen0-3) state-enable registers
> must be provided."
>
> Add ssstateen as a nam
On Mon, Nov 11, 2024 at 4:39 PM Zhenzhong Duan wrote:
>
> Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities
> related to scalable mode translation, thus there are multiple combinations.
>
> This vIOMMU implementation wants to simplify it with a new property "x-flts".
> Wh
On Mon, Nov 11, 2024 at 4:39 PM Zhenzhong Duan wrote:
>
> According to VTD spec, stage-1 page table could support 4-level and
> 5-level paging.
>
> However, 5-level paging translation emulation is unsupported yet.
> That means the only supported value for aw_bits is 48. So default
> aw_bits to 48
On Mon, Nov 11, 2024 at 4:39 PM Zhenzhong Duan wrote:
>
> From: Clément Mathieu--Drif
>
> Signed-off-by: Clément Mathieu--Drif
> Signed-off-by: Zhenzhong Duan
> ---
Acked-by: Jason Wang
Thanks
On Mon, Nov 11, 2024 at 4:39 PM Zhenzhong Duan wrote:
>
> Signed-off-by: Zhenzhong Duan
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Jason Wang
Thanks
Add a CPU entry for the RV64 XiangShan NANHU CPU which
supports single-core and dual-core configurations. More
details can be found at
https://docs.xiangshan.cc/zh-cn/latest/integration/overview
Signed-off-by: MollyChen
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 29
Hi Bernhard,
> Subject: Re: [PATCH v2 3/6] hw:sdhci: Introduce a new "capareg" class member
> to set the different Capability Registers.
> Am 3. Dezember 2024 02:14:57 UTC schrieb Jamin Lin via
> :
> >Currently, it set the hardcode value of capability registers to all
> >ASPEED SOCs However, the
Signed-off-by: MollyChen
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 29 +
2 files changed, 30 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 62115375cd..8f6fac463c 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/risc
On Thu, Oct 17, 2024 at 2:39 PM LIU Zhiwei wrote:
>
>
> On 2024/10/17 11:52, Richard Henderson wrote:
> > On 10/16/24 19:57, LIU Zhiwei wrote:
> >> Hi Richard,
> >>
> >> On 2024/10/17 02:38, Richard Henderson wrote:
> >>> 2595: if (dec->cfg->ext_zcmop) {
> >>> 2690:if (dec->cfg->ex
On Wed, Dec 4, 2024 at 5:09 AM Philippe Mathieu-Daudé wrote:
>
> 2 trivial RISC-V oriented patches extracted from a bigger
> series which refactor include/exec/ headers.
>
> Philippe Mathieu-Daudé (2):
> target/riscv: Include missing headers in 'vector_internals.h'
> target/riscv: Include miss
On Tue, Dec 3, 2024 at 12:39 PM Fea.Wang wrote:
>
> The Svukte ISA extension has been approved for fast-track development.
> https://lf-riscv.atlassian.net/browse/RVS-2977
> And there are Linux patches for the Svukte that are under review.
> https://lore.kernel.org/kvm/20240920-dev-maxh-svukte-reb
On Wed, Dec 4, 2024 at 5:09 AM Philippe Mathieu-Daudé wrote:
>
> Rather than relying on implicit includes, explicit them,
> in order to avoid when refactoring unrelated headers:
>
> target/riscv/internals.h:49:15: error: use of undeclared identifier 'PRV_S'
> 49 | ret = PRV_S;
>
On Wed, Dec 4, 2024 at 5:09 AM Philippe Mathieu-Daudé wrote:
>
> Rather than relying on implicit includes, explicit them,
> in order to avoid when refactoring unrelated headers:
>
> target/riscv/vector_internals.h:36:12: error: call to undeclared function
> 'FIELD_EX32'; ISO C99 and later do no
This patch allows a CXL type3 device to be initialized with zero memory
size, when there is no memory device property provided.
Signed-off-by: Hongjian Fan
---
hw/mem/cxl_type3.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_t
From: Hao Xiang
Multifd sender path gets an array of pages queued by the migration
thread. It performs zero page checking on every page in the array.
The pages are classfied as either a zero page or a normal page. This
change uses Intel DSA to offload the zero page checking from CPU to
the DSA ac
From: Hao Xiang
* Create a dedicated thread for DSA task completion.
* DSA completion thread runs a loop and poll for completed tasks.
* Start and stop DSA completion thread during DSA device start stop.
User space application can directly submit task to Intel DSA
accelerator by writing to DSA's
From: Hao Xiang
* Test DSA start and stop path.
* Test DSA configure and cleanup path.
* Test DSA task submission and completion path.
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
tests/unit/meson.build | 6 +
tests/unit/test-dsa.c | 503 +
From: Hao Xiang
Intel DSA offloading is an optional feature that turns on if
proper hardware and software stack is available. To turn on
DSA offloading in multifd live migration by setting:
zero-page-detection=dsa-accel
accel-path="dsa: dsa:[dsa_dev_path2] ..."
This feature is turned off by def
From: Hao Xiang
Enable instruction set enqcmd in build.
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
Reviewed-by: Fabiano Rosas
---
meson.build | 14 ++
meson_options.txt | 2 ++
scripts/meson-buildoptions.sh | 3 +++
3 files changed, 19 ins
Signed-off-by: Yichen Wang
Reviewed-by: Fabiano Rosas
---
scripts/update-linux-headers.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
index 99a8d9fa4c..9128c7499b 100755
--- a/scripts/update-linux-headers.s
From: Hao Xiang
* Add a DSA task completion callback.
* DSA completion thread will call the tasks's completion callback
on every task/batch task completion.
* DSA submission path to wait for completion.
* Implement CPU fallback if DSA is not able to complete the task.
Signed-off-by: Hao Xiang
S
From: Yuan Liu
Signed-off-by: Yuan Liu
Signed-off-by: Yichen Wang
Reviewed-by: Fabiano Rosas
---
.../migration/dsa-zero-page-detection.rst | 290 ++
docs/devel/migration/features.rst | 1 +
2 files changed, 291 insertions(+)
create mode 100644 docs/devel/mig
v8
* Rebase on top of 1cf9bc6eba7506ab6d9de635f224259225f63466;
* Fixed the hmp parsing crash in migrate_set_parameter;
* Addressed initialization/cleanup comments from v7;
v7
* Rebase on top of f0a5a31c33a8109061c2493e475c8a2f4d022432;
* Fix a bug that will crash QEMU when DSA initialization fail
From: Hao Xiang
* Add test case to start and complete multifd live migration with DSA
offloading enabled.
* Add test case to start and cancel multifd live migration with DSA
offloading enabled.
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
Reviewed-by: Fabiano
From: Hao Xiang
* Use a safe thread queue for DSA task enqueue/dequeue.
* Implement DSA task submission.
* Implement DSA batch task submission.
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
Reviewed-by: Fabiano Rosas
---
include/qemu/dsa.h | 29 +++
util/dsa.c | 186 ++
From: Hao Xiang
* DSA device open and close.
* DSA group contains multiple DSA devices.
* DSA group configure/start/stop/clean.
Signed-off-by: Hao Xiang
Signed-off-by: Bryan Zhang
Signed-off-by: Yichen Wang
---
include/qemu/dsa.h | 99
util/dsa.c | 280 +
From: Hao Xiang
Create DSA task with operation code DSA_OPCODE_COMPVAL.
Here we create two types of DSA tasks, a single DSA task and
a batch DSA task. Batch DSA task reduces task submission overhead
and hence should be the default option. However, due to the way DSA
hardware works, a DSA batch ta
On Mon, Nov 11, 2024 at 4:38 PM Zhenzhong Duan wrote:
>
> Per VT-d spec 4.1 section 3.15, "Untranslated requests and translation
> requests that result in an address in the interrupt range will be
> blocked with condition code LGN.4 or SGN.8."
>
> This applies to both stage-1 and stage-2 IOMMU pag
ACPI hotplug with 255 or less vCPUs can use the legacy CPU hotplug interface,
which does
not support hotunplug. If it's available, hotunplug will use the modern CPU
hotplug interface.
This creates a situation where hotplug and hotunplug are using different
interfaces, but
the end result is still
Setting a new pending event will clear a previously pending event
of the opposite type, for a given vCPU.
Intuitively, a physical CPU cannot be in the process of both
hotplugging and hot-unplugging at the same time.
Signed-off-by: Eric Mackay
---
hw/acpi/cpu.c | 36 +
On Wed, Nov 27, 2024 at 07:40:39PM +0200, Andrey Drobyshev wrote:
> On 11/25/24 7:07 PM, Peter Xu wrote:
> > On Mon, Nov 25, 2024 at 11:46:11AM -0300, Fabiano Rosas wrote:
> >> Currently a VM that has been target of a migration using
> >> late-block-activate will crash at the end of a new migration
From: Fabiano Rosas
Add a framework for running migrations back and forth between two
guests (aka ping-pong migration). We have seen a couple of bugs that
only reproduce when a guest is migrated and the destination machine is
used as the source of a new migration.
Add a simple test that does 2 m
When migration is either cancelled or failed during switchover, especially
when after the disks are inactivated, QEMU needs to remember re-activate
the disks again before vm starts.
It used to be done separately in two paths: one in qmp_migrate_cancel(),
the other one in the failure path of migrat
Postcopy also has similar error handling for re-activation of block
devices. Use the same API as precopy to do the re-activation, for both src
& dst sides.
Signed-off-by: Peter Xu
---
migration/migration.c | 22 +++---
migration/savevm.c| 10 --
2 files changed, 7 in
Extend the usage of such API to the receiver side, because such status
maintenance is also necessary there.
It's needed to avoid bdrv_inactivate_all() not being invoked when the
drives are already inactive. When invoked, it can crash QEMU. See the
issue link for more information.
So it means we
From: Fabiano Rosas
We don't always want to cleanup both VMs at the same time. One example
is the multifd cancel test, where there's a second migration reusing
the source VM. The next patches will add another instance, keeping the
destination VM instead.
Extract the cleanup routine from test_mig
From: Fabiano Rosas
Stop using hardcoded strings for -serial so we can in the next patches
perform more than one migration in a row. Having the serial path
hardcoded means we cannot reuse the code when dst becomes the new src.
Signed-off-by: Fabiano Rosas
Link: https://lore.kernel.org/r/2024112
In 99% cases, after QEMU migrates to dest host, it tries to detect the
target VM runstate using global_state_get_runstate().
There's one outlier so far which is Xen that won't send global state.
That's the major reason why global_state_received() check was always there
together with global_state_g
I started looking at this problem as a whole when reviewing Fabiano's
series, especially the patch (for a QEMU crash [1]):
https://lore.kernel.org/r/20241125144612.16194-5-faro...@suse.de
The proposed patch could work, but it's unwanted to add such side effect to
migration. So I start to think a
Migration capability 'late-block-active' controls when the block drives
will be activated. If enabled, block drives will only be activated until
VM starts, either src runstate was "live" (RUNNING, or SUSPENDED), or it'll
be postponed until qmp_cont().
Let's do this unconditionally. There's no ha
From: Fabiano Rosas
The only_target option's purpose is to make sure only the destination
QTestState machine is initialized. This allows the test code to retain
an already initialized source machine (e.g. for doing ping pong
migration).
We have drifted from that a bit when adding new code, so mo
Postcopy never cared about late-block-active. However there's no mention
in the capability that it doesn't apply to postcopy.
Considering that we _assumed_ late activation is always good, do that too
for postcopy unconditionally, just like precopy. After this patch, we
should have unified the be
Src QEMU sets block_inactive=true very early before the invalidation takes
place. It means if something wrong happened during setting the flag but
before reaching qemu_savevm_state_complete_precopy_non_iterable() where it
did the invalidation work, it'll make block_inactive flag inconsistent.
For
> -Original Message-
> From: Brian Cain
> Sent: Tuesday, December 3, 2024 1:28 PM
> To: Anton Johansson ; Richard Henderson
>
> Cc: qemu-devel@nongnu.org; a...@rev.ng; ltaylorsimp...@gmail.com;
> bc...@quicinc.com; phi...@linaro.org; alex.ben...@linaro.org
> Subject: Re: [RFC PATCH v1
From: Kaiwen Xue
This adds definitions for counter delegation, including the new
scountinhibit register and the mstateen.CD bit.
Signed-off-by: Kaiwen Xue
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 8 +++-
target/
As per the ratified AIA spec v1.0, three stateen bits control AIA CSR
access.
Bit 60 controls the indirect CSRs
Bit 59 controls the most AIA CSR state
Bit 58 controls the IMSIC state such as stopei and vstopei
Enable the corresponding bits in [m|h]stateen and enable corresponding
checks in the CS
From: Kaiwen Xue
This adds the indirect access registers required by sscsrind/smcsrind
and the operations on them. Note that xiselect and xireg are used for
both AIA and sxcsrind, and the behavior of accessing them depends on
whether each extension is enabled and the value stored in xiselect.
Co
This series adds the counter delegation extension support. The counter
delegation ISA extension(Smcdeleg/Ssccfg) actually depends on multiple ISA
extensions.
1. S[m|s]csrind : The indirect CSR extension[1] which defines additional
5 ([M|S|VS]IREG2-[M|S|VS]IREG6) register to address size limitat
Add configuration options so that they can be enabled/disabld from
qemu commandline.
Acked-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
The counter delegation/configuration extensions depend on the following
extensions.
1. Smcdeleg - To enable counter delegation from M to S
2. S[m|s]csrind - To enable indirect access CSRs
Add an implied rule so that these extensions are enabled by default
if the sscfg extension is enabled.
Revie
From: Kaiwen Xue
Since xiselect and xireg also will be of use in sxcsrind, AIA should
have its own separated interface when those CSRs are accessed.
Signed-off-by: Kaiwen Xue
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
target/riscv/csr.c | 165 +++
From: Kaiwen Xue
This adds the properties for sxcsrind. Definitions of new registers and
implementations will come with future patches.
Signed-off-by: Kaiwen Xue
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 2 ++
The dependant ISA features are enabled at the end of cpu_realize
in finalize_features. Thus, PMU init should be invoked after that
only. Move the init invocation to riscv_tcg_cpu_finalize_features.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
target/riscv/tcg/tcg-cpu.c | 28
From: Kaiwen Xue
This adds checks in ops performed on xireg and xireg2-xireg6 so that the
counter delegation function will receive a valid xiselect value with the
proper extensions enabled.
Co-developed-by: Atish Patra
Signed-off-by: Kaiwen Xue
Reviewed-by: Alistair Francis
Signed-off-by: Ati
This adds the properties for counter delegation ISA extensions
(Smcdeleg/Ssccfg). Definitions of new registers and and implementation
will come in the next set of patches.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h |
From: Kaiwen Xue
The Smcdeleg/Ssccfg adds the support for counter delegation via
S*indcsr and Ssccfg.
It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE)
to enable this extension and scountovf virtualization.
Signed-off-by: Kaiwen Xue
Co-developed-by: Atish Patra
Signed-o
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
fourth release candidate for the QEMU 9.2 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu.org/qemu-9.2.0-rc3.tar.xz
http://download.qemu
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