Re: [PATCH v6 07/60] kvm: Introduce kvm_arch_pre_create_vcpu()

Hi, On 5/11/24 06:23, Xiaoyao Li wrote: Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent work prior to create any vcpu. This is for i386 TDX because it needs call TDX_INIT_VM before creating any vcpu. Signed-off-by: Xiaoyao Li Acked-by: Gerd Hoffmann --- Changes in v3: - pass @

Re: [PATCH v5 17/20] tests/acpi: q35: Update host address width in DMAR

Hi Zhenzhong, Ack >cmd On 11/11/2024 09:34, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Differences: > > @@ -1,39 +1,39 @@ > /* >* Intel ACPI Component Arch

Re: [RFC PATCH 08/11] rust: build: establish a baseline of lints across all crates

Paolo Bonzini writes: > Many lints that default to allow can be helpful in detecting bugs or > keeping the code style homogeneous. Add them liberally, though perhaps > not as liberally as in hw/char/pl011/src/lib.rs. In particular, enabling > entire groups can be problematic because of bitrot

Re: [PATCH] hw/openrisc: Fixed undercounting of TTCR in continuous mode

On Fri, Jun 07, 2024 at 03:29:33PM -0700, Joel Holdsworth via wrote: > In the existing design, TTCR is prone to undercounting when running in > continuous mode. This manifests as a timer interrupt appearing to > trigger a few cycles prior to the deadline set in SPR_TTMR_TP. > > When the timer trig

Re: [PATCH RFC 0/5] Change ghes driver to use HEST-based offsets

Em Wed, 2 Oct 2024 15:45:34 +0200 Igor Mammedov escreveu: > On Tue, 1 Oct 2024 13:42:45 +0200 > Mauro Carvalho Chehab wrote: > > > This RFC series was part of the previous PR to add generic error injection > > support on GHES. > > > > It contains only the changes of the math used to calculate

Re: [PATCH RFC 0/5] Change ghes driver to use HEST-based offsets

Em Wed, 13 Nov 2024 07:54:18 +0100 Mauro Carvalho Chehab escreveu: > Em Wed, 2 Oct 2024 15:45:34 +0200 > Igor Mammedov escreveu: > > > On Tue, 1 Oct 2024 13:42:45 +0200 > > Mauro Carvalho Chehab wrote: > > > > > This RFC series was part of the previous PR to add generic error injection > >

Re: [RFC v3 3/3] vhost: Allocate memory for packed vring

Hi, On 10/28/24 11:07 AM, Sahil Siddiq wrote: [...] The payload that VHOST_SET_VRING_BASE accepts depends on whether split virtqueues or packed virtqueues are used [6]. In hw/virtio/vhost- vdpa.c:vhost_vdpa_svq_setup() [7], the following payload is used which is not suitable for packed virtqueu

[PATCH 1/2] Add RW support for 4k sector size vhdx

Signed-off-by: Takeshi Suzuki --- block/vhdx.c | 76 +++- 1 file changed, 70 insertions(+), 6 deletions(-) diff --git a/block/vhdx.c b/block/vhdx.c index 5aa1a13506..495ddc2815 100644 --- a/block/vhdx.c +++ b/block/vhdx.c @@ -824,8 +824,8 @@ vhdx_p

[PATCH 0/2] Add RW support for 4k sector size vhdx

The first patch adds support to read and write VHDX images with 4k logical sector sizes. This is done by internally converting bdrv sectors of size 512 to logical sectors. VHDX image creation with 4k logical sector size is NOT implemented. The second patch adds an iotest which reads and writes to

[PATCH 2/2] Add iotest for 4k sector size vhdx

See https://github.com/takeshibaconsuzuki/qemu/blob/vhdx_4k_rw/tests/qemu-iotests/sample_images/4k.vhdx.bz2 for binary file. Signed-off-by: Takeshi Suzuki --- tests/qemu-iotests/315 | 65 +++ tests/qemu-iotests/315.out | 20 ++ tests/

Re: [PATCH 3/7] target/i386/kvm: init PMU information only once

Hi Zhao, On 11/10/24 7:29 AM, Zhao Liu wrote: > Hi Dongli, > >> int kvm_arch_init_vcpu(CPUState *cs) >> { >> struct { >> @@ -2237,6 +2247,13 @@ int kvm_arch_init_vcpu(CPUState *cs) >> cpuid_i = kvm_x86_build_cpuid(env, cpuid_data.entries, cpuid_i); >> cpuid_data.cpuid.nent = cpui

Re: [PATCH 1/1] vfio/platform: Add mmio-base property to define start address for MMIO mapping

On Tue, 12 Nov 2024 22:02:12 + Juan Pablo Ruiz wrote: > Some platform devices have large MMIO regions (e.g., GPU reserved memory). For > certain devices, it's preferable to have a 1:1 address translation in the VM > to > avoid modifying driver source code. Why do we need 1:1 mappings? Shou

Re: [RFC PATCH 0/5] hw/arm/virt: Add support for user-creatable nested SMMUv3

On Fri, Nov 08, 2024 at 12:52:37PM +, Shameer Kolothum wrote: > Few ToDos to note, > 1. At present default-bus-bypass-iommu=on should be set when >arm-smmuv3-nested dev is specified. Otherwise you may get an IORT >related boot error. Requires fixing. > 2. Hot adding a device is not wor

[PATCH 1/1] vfio/platform: Add mmio-base property to define start address for MMIO mapping

Some platform devices have large MMIO regions (e.g., GPU reserved memory). For certain devices, it's preferable to have a 1:1 address translation in the VM to avoid modifying driver source code. This patch: 1. Increases the VFIO platform bus size from 32MB to 130GB. 2. Changes the mmio_size prope

Re: [PATCH v2 6/7] hostmem: Handle remapping of RAM

On 12.11.24 19:17, William Roche wrote: On 11/12/24 14:45, David Hildenbrand wrote: On 07.11.24 11:21, “William Roche wrote: From: David Hildenbrand Let's register a RAM block notifier and react on remap notifications. Simply re-apply the settings. Warn only when something goes wrong. Note:

Re: [PATCH v2 3/7] accel/kvm: Report the loss of a large memory page

On 12.11.24 19:17, William Roche wrote: On 11/12/24 12:13, David Hildenbrand wrote: On 07.11.24 11:21, “William Roche wrote: From: William Roche When an entire large page is impacted by an error (hugetlbfs case), report better the size and location of this large memory hole, so give a warning

Re: [PATCH v2 2/7] system/physmem: poisoned memory discard on reboot

For shared memory we really need it. Private file-backed is weird ... because we don't know if the shared or the private page is problematic ... :( I agree with you, and we have to decide when should we bail out if ram_block_discard_range() doesn't work. According to me, if discard doesn't wor

Re: [PATCH v2 1/7] accel/kvm: Keep track of the HWPoisonPage page_size

On 12.11.24 19:17, William Roche wrote: On 11/12/24 11:30, David Hildenbrand wrote: On 07.11.24 11:21, “William Roche wrote: From: William Roche When a memory page is added to the hwpoison_page_list, include the page size information.  This size is the backend real page size. To better deal w

Re: [PATCH] GTM19-448: Fix script to work without realpath

Aleksandar Rakic writes: > The archive-source.sh script depends on realpath command, which was > introduced in coreutils-8.15. CentOS-6 build systems use coreutils-4.7, > which does not have realpath, so fix the script to use 'readlink -e' to > perform the same action. Isn't CentOS-6 outside of

[PATCH v4 2/3] plugins: detect qemu plugin API symbols from header

Instead of using a static file (error prone and hard to keep in sync), we generate it using a script. Note: if a symbol is not exported, we'll now notice it when linking for Windows/MacOS platforms. Signed-off-by: Pierrick Bouvier --- MAINTAINERS| 1 + plugins/meson.build

[PATCH v4 3/3] plugins: eradicate qemu-plugins.symbols static file

Signed-off-by: Pierrick Bouvier --- plugins/qemu-plugins.symbols | 59 1 file changed, 59 deletions(-) delete mode 100644 plugins/qemu-plugins.symbols diff --git a/plugins/qemu-plugins.symbols b/plugins/qemu-plugins.symbols deleted file mode 100644 index 032

Re: [PATCH v3 0/3] plugins: generate list of symbols automatically

On 11/12/24 13:08, Alex Bennée wrote: Pierrick Bouvier writes: Now that meson build for plugins was merged, we can cleanup another part with the symbols file. It has to be kept in sync between the header (qemu-plugin.h) and the symbols file. This has proved to be error prone and tedious. We s

[PATCH v4 1/3] plugins: add missing export for qemu_plugin_num_vcpus

Fixes: 4a448b148ca ("plugins: add qemu_plugin_num_vcpus function") Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Pierrick Bouvier --- include/qemu/qemu-plugin.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h index 622c9a02327..0fb

[PATCH v4 0/3] plugins: generate list of symbols automatically

Now that meson build for plugins was merged, we can cleanup another part with the symbols file. It has to be kept in sync between the header (qemu-plugin.h) and the symbols file. This has proved to be error prone and tedious. We solve this by generating this list from header directly using a pytho

Re: [PATCH v3 0/3] plugins: generate list of symbols automatically

Pierrick Bouvier writes: > Now that meson build for plugins was merged, we can cleanup another part with > the symbols file. > It has to be kept in sync between the header (qemu-plugin.h) and the symbols > file. This has proved to be error prone and tedious. > > We solve this by generating this l

Re: [PATCH v2] tests/tcg: Stop using exit() in the gdbstub testcases

Ilya Leoshkevich writes: > GDB 15 does not like exit() anymore: > > (gdb) python exit(0) > Python Exception : 0 > Error occurred in Python: 0 > > Use the GDB's own exit command, like it's already done in a couple > places, everywhere. This is the same fix as commit 93a3048dcf45 > ("te

[PATCH 2/6] linux-user: Drop image_info.alignment

This field is write-only. Use only the function-local variable within load_elf_image. Signed-off-by: Richard Henderson --- linux-user/qemu.h| 1 - linux-user/elfload.c | 7 +++ 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 895

[PATCH 1/6] linux-user: Honor elf alignment when placing images

Most binaries don't actually depend on more than page alignment, but any binary can request it. Not honoring this was a bug. This became obvious when gdb reported Failed to read a valid object file image from memory when examining some vdso which are marked as needing more than page alignme

[PATCH 6/6] linux-user/ppc: Reduce vdso alignment to 4k

Signed-off-by: Richard Henderson --- linux-user/ppc/Makefile.vdso | 6 -- linux-user/ppc/vdso-32.so| Bin 3020 -> 3020 bytes linux-user/ppc/vdso-64.so| Bin 3896 -> 3896 bytes linux-user/ppc/vdso-64le.so | Bin 3896 -> 3896 bytes 4 files changed, 4 insertions(+), 2 deletions(-) di

[PATCH 3/6] linux-user/aarch64: Reduce vdso alignment to 4k

Signed-off-by: Richard Henderson --- linux-user/aarch64/Makefile.vdso | 5 +++-- linux-user/aarch64/vdso-be.so| Bin 3224 -> 3224 bytes linux-user/aarch64/vdso-le.so| Bin 3224 -> 3224 bytes 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/linux-user/aarch64/Makefile.vdso

[PATCH 4/6] linux-user/arm: Reduce vdso alignment to 4k

Signed-off-by: Richard Henderson --- linux-user/arm/Makefile.vdso | 2 +- linux-user/arm/vdso-be.so| Bin 2648 -> 2648 bytes linux-user/arm/vdso-le.so| Bin 2648 -> 2648 bytes 3 files changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/arm/Makefile.vdso b/linux-user/arm/Make

[PATCH 5/6] linux-user/loongarch64: Reduce vdso alignment to 4k

Signed-off-by: Richard Henderson --- linux-user/loongarch64/Makefile.vdso | 3 ++- linux-user/loongarch64/vdso.so | Bin 3560 -> 3560 bytes 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/linux-user/loongarch64/Makefile.vdso b/linux-user/loongarch64/Makefile.vdso index 369d

[PATCH for-9.2 0/6] linux-user: Fix elf load and vdso alignment

GDB picked up that we weren't properly honoring alignment. After fixing that, reduce vdso alignment to minimum page size. r~ Richard Henderson (6): linux-user: Honor elf alignment when placing images linux-user: Drop image_info.alignment linux-user/aarch64: Reduce vdso alignment to 4k l

[PATCH 01/20] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit

All these MemoryRegionOps read() and write() handlers are implemented expecting 32-bit accesses. Clarify that setting .impl.min/max_access_size fields. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- hw/char/xilinx_uartlite.c | 4 hw/intc/xilinx_intc.c | 4

[PATCH 08/20] hw/net/xilinx_ethlite: Add addr_to_port_index() helper

For a particular physical address within the EthLite MMIO range, addr_to_port_index() returns which port is accessed. Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/x

Re: [PATCH] GTM19-448: Fix script to work without realpath

On 11/12/24 10:38, Aleksandar Rakic wrote: The archive-source.sh script depends on realpath command, which was introduced in coreutils-8.15. CentOS-6 build systems use coreutils-4.7, which does not have realpath, so fix the script to use 'readlink -e' to perform the same action. Centos 6 is not

[RESEND PATCH 08/10] aspeed: Add uhci support for ast2400 and ast2500

Add UHCI support for ast2400 and ast2500 SoCs. With this patch, the UHCI port is successfully enabled on the ast2500-evb machine. Note that the EHCI controller on AST2400 and AST2500 does not support companion mode, so the UHCI controller is instantiated as stand-alone device and creates an additi

Re: [PATCH v3 4/4] target/mips: Enable MSA ASE for mips64R2-generic

On 12/11/24 16:41, Aleksandar Rakic wrote: Enable MSA ASE for mips64R2-generic CPU. Cherry-picked 60f6ae8d3d685ba1ea5d301222fb72b67f39264f from https://github.com/MIPS/gnutools-qemu Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- target/mips/cpu-defs.c.inc | 4 +++- 1

Re: [PATCH v2 3/6] target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument

On 11/12/24 09:20, Philippe Mathieu-Daudé wrote: Having the callee add 1 to shift amount is misleading (see the NM_LSA case in decode_nanomips_32_48_opc() where we have to manually substract 1). Rather have the callers pass a modified $sa. Suggested-by: Richard Henderson Signed-off-by: Philippe

[PATCH 12/20] hw/net/xilinx_ethlite: Access TX_GIE register for each port

Rather than accessing the registers within the mixed RAM/MMIO region as indexed register, declare a per-port TX_GIE. This will help to map the RAM as RAM (keeping MMIO as MMIO) in few commits. Previous s->regs[R_TX_GIE0] and s->regs[R_TX_GIE1] are now unused. Not a concern, this array will soon di

Re: [RFC PATCH 01/11] rust: qemu_api: do not disable lints outside bindgen-generated code

On 11/12/24 11:10, Junjie Mao wrote: diff --git a/meson.build b/meson.build index 1239f5c48c..8cea09ffe1 100644 --- a/meson.build +++ b/meson.build @@ -4,6 +4,7 @@ project('qemu', ['c'], meson_version: '>=1.5.0', version: files('VERSION')) meson.add_devenv({ 'MESON_BUILD_ROOT' : meso

[PATCH] GTM19-448: Fix script to work without realpath

The archive-source.sh script depends on realpath command, which was introduced in coreutils-8.15. CentOS-6 build systems use coreutils-4.7, which does not have realpath, so fix the script to use 'readlink -e' to perform the same action. Cherry-picked 5d1d5766f0219ce2bec4e41c2467317df920ec0a and 80

Re: [PATCH v2 1/6] target/mips: Introduce decode tree bindings for microMIPS ISA

On 11/12/24 09:20, Philippe Mathieu-Daudé wrote: From: Philippe Mathieu-Daudé Introduce the microMIPS decodetree configs for the 16-bit and 32-bit instructions. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 2 ++ target/mips/tcg/micromips16.decode

[PATCH 13/20] hw/net/xilinx_ethlite: Access TX_LEN register for each port

Rather than accessing the registers within the mixed RAM/MMIO region as indexed register, declare a per-port TX_LEN. This will help to map the RAM as RAM (keeping MMIO as MMIO) in few commits. Previous s->regs[R_TX_LEN0] and s->regs[R_TX_LEN1] are now unused. Not a concern, this array will soon di

Re: [RFC 18/21] arm/cpu: Introduce a customizable kvm host cpu model

Hi Conny, On 11/12/24 17:30, Cornelia Huck wrote: > On Mon, Nov 11 2024, Cornelia Huck wrote: > >> On Mon, Nov 04 2024, Eric Auger wrote: >> >>> Hi Daniel, >>> >>> On 10/28/24 18:04, Daniel P. Berrangé wrote: On Mon, Oct 28, 2024 at 04:48:18PM +, Peter Maydell wrote: > On Mon, 28 Oc

Ping: [PATCH v2] tests/tcg: Stop using exit() in the gdbstub testcases

On Tue, 2024-10-22 at 13:37 +0200, Ilya Leoshkevich wrote: > GDB 15 does not like exit() anymore: > >     (gdb) python exit(0) >     Python Exception : 0 >     Error occurred in Python: 0 > > Use the GDB's own exit command, like it's already done in a couple > places, everywhere. This is the same

Re: [PATCH v2 4/6] target/mips: Decode LSA shift amount using decodetree function

On 11/12/24 09:20, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 3 ++- target/mips/tcg/rel6.decode | 4 +++- target/mips/tcg/msa_translate.c | 4 ++-- target/mips/tcg/rel6_translate.c | 9 +++-- 4 files changed, 14 ins

Re: [PATCH v2 3/7] accel/kvm: Report the loss of a large memory page

On 11/12/24 12:13, David Hildenbrand wrote: On 07.11.24 11:21, “William Roche wrote: From: William Roche When an entire large page is impacted by an error (hugetlbfs case), report better the size and location of this large memory hole, so give a warning message when this page is first hit: Mem

Re: [PATCH v2 2/7] system/physmem: poisoned memory discard on reboot

On 11/12/24 12:07, David Hildenbrand wrote: On 07.11.24 11:21, “William Roche wrote: From: William Roche We take into account the recorded page sizes to repair the memory locations, calling ram_block_discard_range() to punch a hole in the backend file when necessary and regenerate a usable mem

Re: [PATCH v2 6/6] target/mips: Convert nanoMIPS LSA opcode to decodetree

On 11/12/24 09:20, Philippe Mathieu-Daudé wrote: From: Philippe Mathieu-Daudé Simply call the generic gen_lsa() helper. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/nanomips32.decode| 6 ++ target/mips/tcg/nanomips_translate.c

Re: [PATCH v2 1/7] accel/kvm: Keep track of the HWPoisonPage page_size

On 11/12/24 11:30, David Hildenbrand wrote: On 07.11.24 11:21, “William Roche wrote: From: William Roche When a memory page is added to the hwpoison_page_list, include the page size information.  This size is the backend real page size. To better deal with hugepages, we create a single entry f

Re: [PATCH v2 6/7] hostmem: Handle remapping of RAM

On 11/12/24 14:45, David Hildenbrand wrote: On 07.11.24 11:21, “William Roche wrote: From: David Hildenbrand Let's register a RAM block notifier and react on remap notifications. Simply re-apply the settings. Warn only when something goes wrong. Note: qemu_ram_remap() will not remap when RAM_

Re: [PATCH v2 5/6] target/mips: Convert microMIPS LSA opcode to decodetree

On 11/12/24 09:20, Philippe Mathieu-Daudé wrote: Simply call the generic gen_lsa(), using the plus_1() helper to add 1 to the shift amount. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/micromips32.decode| 8 target/mips/tcg/micromips_translate.c | 10 ++

[PATCH 15/20] hw/net/xilinx_ethlite: Map RX_CTRL as MMIO

Declare RX registers as MMIO region, split it out of the current mixed RAM/MMIO region. The memory flat view becomes: FlatView #0 Root memory region: system 8100-810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 810007e4-810007f3 (prio 0, i/o): ethlite.

[PATCH 19/20] hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory region

Rather than using I/O registers for RAM buffer, having to swap endianness back and forth (because the core memory layer automatically swaps endiannes for us), declare the buffers as RAM regions. Remove the now unused s->regs[] array. The memory flat view becomes: FlatView #0 Root memory regi

[PATCH 04/20] hw/net/xilinx_ethlite: Update QOM style

Use XlnxXpsEthLite typedef, OBJECT_DECLARE_SIMPLE_TYPE macro; convert type_init() to DEFINE_TYPES(). Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 48 +++-- 1 file changed, 22 insertions(+), 26 deletions(-) diff --git a/hw/net/xilinx_eth

[PATCH 09/20] hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper

txbuf_ptr() points to the beginning of a (RAM) TX buffer within the device state. Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index fe9189131

[PATCH 16/20] hw/net/xilinx_ethlite: Map TX_LEN as MMIO

Declare TX registers as MMIO region, split it out of the current mixed RAM/MMIO region. Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 71 ++--- 1 file changed, 59 insertions(+), 12 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/n

[PATCH 11/20] hw/net/xilinx_ethlite: Access RX_CTRL register for each port

Rather than accessing the registers within the mixed RAM/MMIO region as indexed register, declare a per-port RX_CTRL. This will help to map the RAM as RAM (keeping MMIO as MMIO) in few commits. Previous s->regs[R_RX_CTRL0] and s->regs[R_RX_CTRL1] are now unused. Not a concern, this array will soon

[PATCH 18/20] hw/net/xilinx_ethlite: Map TX_CTRL as MMIO

Add TX_CTRL to the TX registers MMIO region. Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 56 +++-- 1 file changed, 26 insertions(+), 30 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index f7a5b1620a..f681b

[PATCH 17/20] hw/net/xilinx_ethlite: Map TX_GIE as MMIO

Add TX_GIE to the TX registers MMIO region. Before TX_GIE1 was accessed as RAM, with no effect. Now it is accessed as MMIO, also without any effect. Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 17 +++-- 1 file changed, 7 insertions(+), 10 deletions(-) diff -

[PATCH 14/20] hw/net/xilinx_ethlite: Access TX_CTRL register for each port

Rather than accessing the registers within the mixed RAM/MMIO region as indexed register, declare a per-port TX_CTRL. This will help to map the RAM as RAM (keeping MMIO as MMIO) in few commits. Previous s->regs[R_TX_CTRL0] and s->regs[R_TX_CTRL1] are now unused. Not a concern, this array will soon

[PATCH 20/20] hw/net/xilinx_ethlite: Rename 'mmio' MR as 'container'

Having all its address range mapped by subregions, s->mmio MemoryRegion effectively became a container. Rename it as 'container' for clarity. Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/

[PATCH 07/20] hw/net/xilinx_ethlite: Rename rxbuf -> port_index

'rxbuf' is the index of the port used. Rename it as 'port_index'. Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 76b1e7d826..20919b4f54 10064

[PATCH 10/20] hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helper

rxbuf_ptr() points to the beginning of a (RAM) RX buffer within the device state. Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index d4882f43f7..fdbf

[PATCH 05/20] hw/net/xilinx_ethlite: Correct maximum RX buffer size

The current max RX bufsize is set to 0x800. This is invalid, since it contains the MMIO registers region. Add the correct definition and use it. Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/net/xilinx_

[PATCH 06/20] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented)

Rather than handling the MDIO registers as RAM, map them as unimplemented I/O within the device MR. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 8100-810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 810007e4-

[PATCH 02/20] hw/net/xilinx_ethlite: Convert some debug logs to trace events

Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 5 +++-- hw/net/trace-events | 4 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index e84b4cdd35..bb330a233f 100644 --- a/hw/net/xilinx_ethlite.c +++ b/h

[PATCH 00/20] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls

This is the result of a long discussion with Edgar (started few years ago!) and Paolo: https://lore.kernel.org/qemu-devel/34f6fe2f-06e0-4e2a-a361-2d662f681...@redhat.com/ After clarification from Richard on MMIO/RAM accesses, I figured strengthening the model regions would make things obvious, even

[PATCH 03/20] hw/net/xilinx_ethlite: Remove unuseful debug logs

Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 8 1 file changed, 8 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index bb330a233f..2b52597f03 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -32,7 +32,6 @@ #includ

[PATCH 0/7 for-9.2] Fix broken cpu hotplug after migration

1st 4 patches are fixing regression and getting rid of not needed changes that were merged out of context (ARM CPU hotplug) without proper review, by simply reverting offendining patches to keep history clean as patches not 9.2 material to begin with. The rest [5-7/7] are not tested RFC (not for m

[PATCH v3 4/4] target/mips: Enable MSA ASE for mips64R2-generic

Enable MSA ASE for mips64R2-generic CPU. Cherry-picked 60f6ae8d3d685ba1ea5d301222fb72b67f39264f from https://github.com/MIPS/gnutools-qemu Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- target/mips/cpu-defs.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) d

[PATCH v3 0/4] Improve Mips target

This patch series adds support for emulation of CRC32 instructions for the Mips target in QEMU, skips NaN mode check for soft-float, adds a CLI flag for enabling an MSA feature, and enables the MSA for MIPS64R2-generic. There aren't tests for these improvements. The patch 1/8 "Add CP0 MemoryMapID

[RESEND PATCH 06/10] usb/uhci: Add aspeed specific read and write functions

Aspeed uses non-standard UHCI register addresses. On top of that, registers are 32 bit wide instead of 16 bit. Map Aspeed UHCI addresses to standard UHCI addresses and where needed combine/split 32 bit accesses to solve the problem. In addition to that, Aspeed SoCs starting with AST2600 support a

[RESEND PATCH 04/10] usb/uhci: enlarge uhci memory space

hcd-uhci-sysbus will require more memory than hcd-uhci-pci since registers for some hardware (specifically Aspeed) don't map 1:1. Signed-off-by: Guenter Roeck --- Changes since RFC: - Rebased to v9.1.0-1673-g134b443512 hw/usb/hcd-uhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) dif

[PATCH 4/7 for-9.2] tests/acpi: update expected blobs

Expected AML return to the state before bf1ecc8dad606 (w/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states) droping not needed CPRS and _STA logic that broke cpu hotplug @@ -2887,7 +2887,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x0001)

[RESEND PATCH 05/10] usb/uhci: Add support for usb-uhci-sysbus

Signed-off-by: Guenter Roeck --- Changes since RFC: - Rebased to v9.1.0-1673-g134b443512 hw/arm/Kconfig | 1 + hw/usb/Kconfig | 4 ++ hw/usb/hcd-uhci-sysbus.c | 100 +++ hw/usb/hcd-uhci-sysbus.h | 23 + hw/usb/meson.build

[PATCH v2 6/6] target/mips: Convert nanoMIPS LSA opcode to decodetree

From: Philippe Mathieu-Daudé Simply call the generic gen_lsa() helper. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/nanomips32.decode| 6 ++ target/mips/tcg/nanomips_translate.c | 7 +++ target/mips/tcg/nanomips_translate.

[PATCH v3 0/4] Improve Mips target

Aleksandar Rakic (4): Add support for emulation of CRC32 instructions Skip NaN mode check for soft-float target/mips: Enable MSA ASE using a CLI flag target/mips: Enable MSA ASE for mips64R2-generic linux-user/mips/cpu_loop.c | 6 -- target/mips/cpu-defs.c.inc | 4 +++-

[PATCH v3 1/4] Add support for emulation of CRC32 instructions

Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions. Reuse zlib crc32() and Linux crc32c(). Cherry-picked 4cc974938aee1588f852590509004e340c072940 from https://github.com/MIPS/gnutools-qemu Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Aleksandar R

[PATCH v3 2/4] Skip NaN mode check for soft-float

Skip NaN mode check for soft-float since NaN mode is irrelevant if an ELF binary's FPU mode is soft-float, i.e. it doesn't utilize a FPU. Cherry-picked 63492a56485f6b755fccf7ad623f7a189bfc79b6 from https://github.com/MIPS/gnutools-qemu Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Ra

[PATCH v3 3/4] target/mips: Enable MSA ASE using a CLI flag

Enable MSA ASE using a CLI flag -cpu ,msa=on. Signed-off-by: Aleksandar Rakic --- target/mips/cpu.c | 16 target/mips/cpu.h | 1 + target/mips/internal.h | 2 +- 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c inde

[RFC PATCH 03/14] s390x/cpumodel: add msa12 changes

MSA12 changes the KIMD/KLMD instruction format for SHA3/SHAKE. Signed-off-by: Hendrik Brueckner --- target/s390x/cpu_features_def.h.inc | 1 + target/s390x/gen-features.c | 8 2 files changed, 9 insertions(+) diff --git a/target/s390x/cpu_features_def.h.inc b/target/s390x/cpu_

[RFC PATCH 12/14] s390x/cpumodel: correct PLO feature wording

The PLO functions 0, 4, 8, 12, 16, and 20 use 32-bit registers values. The plo-*gr variants use 64-bit instead and, thus, correct the wording. Signed-off-by: Hendrik Brueckner Reviewed-by: Janosch Frank --- target/s390x/cpu_features_def.h.inc | 12 ++-- 1 file changed, 6 insertions(+),

Re: [edk2-devel] [RFC PATCH v2 1/1] hw/arm/sbsa-ref: Support CXL Host Bridge & CFMW

W dniu 7.11.2024 o 13:04, Jonathan Cameron pisze: On Tue, 5 Nov 2024 18:43:46 +0800 "Yuquan Wang" wrote: This creates a default pxb-cxl (bus_nr=0xc0) bridge with two cxl root ports on sbsa-ref. And the memory layout places 64K space for the cxl host bridge register regions(CHBCR) in the sbsa-r

[RFC PATCH 06/14] s390x/cpumodel: add Concurrent-functions facility support

The Concurrent-functions facility introduces the new instruction Perform Functions with Concurrent Results (PFCR) with few subfunctions. Signed-off-by: Hendrik Brueckner --- linux-headers/asm-s390/kvm.h| 3 ++- target/s390x/cpu_features.c | 2 ++ target/s390x/cpu_features.h

[PATCH v2 4/6] target/mips: Decode LSA shift amount using decodetree function

Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 3 ++- target/mips/tcg/rel6.decode | 4 +++- target/mips/tcg/msa_translate.c | 4 ++-- target/mips/tcg/rel6_translate.c | 9 +++-- 4 files changed, 14 insertions(+), 6 deletions(-) diff --git a/target/mips/tcg

[PATCH v2 5/6] target/mips: Convert microMIPS LSA opcode to decodetree

Simply call the generic gen_lsa(), using the plus_1() helper to add 1 to the shift amount. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/micromips32.decode| 8 target/mips/tcg/micromips_translate.c | 10 ++ target/mips/tcg/micromips_translate.c.inc | 5

[PATCH v2 3/6] target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument

Having the callee add 1 to shift amount is misleading (see the NM_LSA case in decode_nanomips_32_48_opc() where we have to manually substract 1). Rather have the callers pass a modified $sa. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa_translate.

[PATCH v2 0/6] target/mips: Convert nanoMIPS LSA opcode to decodetree

Prepare buildsys to decode micro/nanoMIPS opcodes using the decodetree script. Simplify gen_lsa/dsa() and convert micro/nanoMIPS LSA opcode to decodetree. Philippe Mathieu-Daudé (6): target/mips: Introduce decode tree bindings for microMIPS ISA target/mips: Introduce decode tree bindings for n

[PATCH v2 1/6] target/mips: Introduce decode tree bindings for microMIPS ISA

From: Philippe Mathieu-Daudé Introduce the microMIPS decodetree configs for the 16-bit and 32-bit instructions. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 2 ++ target/mips/tcg/micromips16.decode| 9 + target/mips/tcg/micromips32.dec

[PATCH v2 2/6] target/mips: Introduce decode tree bindings for nanoMIPS ISA

From: Philippe Mathieu-Daudé Introduce the nanoMIPS decodetree configs for the 16-bit and 32-bit instructions. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Rikalo Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h

[RFC PATCH 13/14] s390x/cpumodel: Add PLO-extension facility

The PLO-extension facility introduces numerous locking related subfunctions. Signed-off-by: Hendrik Brueckner Reviewed-by: Janosch Frank --- target/s390x/cpu_features_def.h.inc | 39 +++ target/s390x/cpu_models.c | 38 ++ target/s390x/ge

[RFC PATCH 09/14] s390x/cpumodel: add Vector-Packed-Decimal-Enhancement facility 3

This facility introduces new capabilities for the signed-pack-decimal format. Signed-off-by: Hendrik Brueckner --- target/s390x/cpu_features_def.h.inc | 1 + target/s390x/cpu_models.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/s390x/cpu_features_def.h.inc b/target/s3

[RFC 5/7] DO NOT MERGE: acpi: cpuhp: add option to AML genrator to opt-in to always present vCPUs

Looking at [1] what 'present' bit would do, it's no necessary as it's statically defined for VM instance. So instead of introducing new ABI in cpuhp flags register, add CPUHotplugFeatures::always_present_cpus config option, that when set change _STA default return value to always present but not en

[RFC PATCH 01/14] s390x/cpumodel: add msa10 subfunctions

MSA10 introduces new AES XTS subfunctions. Signed-off-by: Hendrik Brueckner --- target/s390x/cpu_features.c | 2 ++ target/s390x/cpu_features_def.h.inc | 6 ++ target/s390x/cpu_models.c | 4 target/s390x/gen-features.c | 20 4 files chan

[RFC PATCH 08/14] s390x/cpumodel: add Miscellaneous-Instruction-Extensions Facility 4

This facility introduces few new instructions. Signed-off-by: Hendrik Brueckner --- target/s390x/cpu_features_def.h.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/s390x/cpu_features_def.h.inc b/target/s390x/cpu_features_def.h.inc index 0b7be0e6e9..8be2e0e46d 100644 --- a/target/

[RFC PATCH 10/14] s390x/cpumodel: add Ineffective-nonconstrained-transaction facility

This facility indicates reduced support for noncontrained transactional-execution. Signed-off-by: Hendrik Brueckner --- target/s390x/cpu_features_def.h.inc | 1 + target/s390x/cpu_models.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/s390x/cpu_features_def.h.inc b/targ

[RESEND PATCH 01/10] usb/uhci: checkpatch cleanup

Fix reported checkpatch issues to prepare for next patches in the series. No functional change. Reviewed-by: Cédric Le Goater Signed-off-by: Guenter Roeck --- Changes since RFC: - Rebased to v9.1.0-1673-g134b443512 - Added Reviewed-by: tag hw/usb/hcd-uhci.c | 90 +-

Re: [PATCH 2/2] target/mips: Convert nanoMIPS LSA opcode to decodetree

On 12/11/24 14:30, Richard Henderson wrote: On 11/11/24 14:44, Philippe Mathieu-Daudé wrote: From: Philippe Mathieu-Daudé Simply call the generic gen_lsa() helper, taking care to substract 1 to the shift field. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé ---

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