Re: [PATCH v2 5/6] target/mips: Convert microMIPS LSA opcode to decodetree

[Richard Henderson]

On 11/12/24 09:20, Philippe Mathieu-Daudé wrote:

Simply call the generic gen_lsa(), using the plus_1()
helper to add 1 to the shift amount.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
  target/mips/tcg/micromips32.decode        |  8 ++++++++
  target/mips/tcg/micromips_translate.c     | 10 ++++++++++
  target/mips/tcg/micromips_translate.c.inc |  5 -----
  3 files changed, 18 insertions(+), 5 deletions(-)

Reviewed-by: Richard Henderson <richard.hender...@linaro.org>

r~

diff --git a/target/mips/tcg/micromips32.decode 
b/target/mips/tcg/micromips32.decode
index c115ed2eab..958883ce84 100644
--- a/target/mips/tcg/micromips32.decode
+++ b/target/mips/tcg/micromips32.decode
@@ -7,3 +7,11 @@
  # Reference: MIPS Architecture for Programmers, Volume II-B
  #            microMIPS32 Instruction Set
  #            (Document Number: MD00582)
+
+&r                  rs rt rd sa
+
+%lsa_sa             9:2  !function=plus_1
+
+@lsa                ...... rt:5  rs:5  rd:5  .. ... ......  &r sa=%lsa_sa
+
+LSA                 000000 ..... ..... ..... .. 000 001111  @lsa
diff --git a/target/mips/tcg/micromips_translate.c 
b/target/mips/tcg/micromips_translate.c
index 49e90e7eca..f0b5dbf655 100644
--- a/target/mips/tcg/micromips_translate.c
+++ b/target/mips/tcg/micromips_translate.c
@@ -9,6 +9,16 @@
  #include "qemu/osdep.h"
  #include "translate.h"

+static inline int plus_1(DisasContext *ctx, int x)

+{
+    return x + 1;
+}
+
  /* Include the auto-generated decoders.  */
  #include "decode-micromips16.c.inc"
  #include "decode-micromips32.c.inc"
+
+static bool trans_LSA(DisasContext *ctx, arg_r *a)
+{
+    return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
+}
diff --git a/target/mips/tcg/micromips_translate.c.inc 
b/target/mips/tcg/micromips_translate.c.inc
index e8ec5a0ff2..4b4550872f 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -191,7 +191,6 @@ enum {
      /* The following can be distinguished by their lower 6 bits. */
      BREAK32 = 0x07,
      INS = 0x0c,
-    LSA = 0x0f,
      ALIGN = 0x1f,
      EXT = 0x2c,
      POOL32AXF = 0x3c,
@@ -1793,10 +1792,6 @@ static void decode_micromips32_opc(CPUMIPSState *env, 
DisasContext *ctx)
          case INS:
              gen_bitops(ctx, OPC_INS, rt, rs, rr, rd);
              return;
-        case LSA:
-            check_insn(ctx, ISA_MIPS_R6);
-            gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) + 1);
-            break;
          case ALIGN:
              check_insn(ctx, ISA_MIPS_R6);
              gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2));