Ping: [PATCH] accel/kvm: check for KVM_CAP_READONLY_MEM on VM

I haven't heard anything about this patch for a while. https://patchew.org/QEMU/20240903062953.3926498-1-erbse...@gmx.de/ From 5c1ad1ff44438402ec824a224ac4659c8044ec7e Mon Sep 17 00:00:00 2001 From: Tom Dohrmann Date: Tue, 3 Sep 2024 06:25:04 + Subject: [PATCH] accel/kvm: check for KVM_CAP_RE

Re: [PATCH v3 03/14] ppc/spapr: remove deprecated machine pseries-2.3

On 10/7/24 17:38, Harsh Prateek Bora wrote: Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.3 specific code with this patch for now. While at it, also remove the dynamic-reconfiguration option which was in

Re: [PATCH v3 04/14] ppc/spapr: remove deprecated machine pseries-2.4

On 10/7/24 17:38, Harsh Prateek Bora wrote: Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.4 specific code with this patch for now. While at it, also remove SpaprMachineClass::dr_lmb_enabled which is now

Re: [PATCH v3 05/14] ppc/spapr: remove deprecated machine pseries-2.5

On 10/7/24 17:38, Harsh Prateek Bora wrote: Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.5 specific code with this patch for now. Also drop sPAPRMachineClass::use_ohci_by_default which is now useless.

Re: [PATCH v3 13/14] ppc/spapr: remove deprecated machine pseries-2.12

On 10/7/24 17:38, Harsh Prateek Bora wrote: Commit 0cac0f1b964 marked pseries-2.12 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.12 specific code with this patch. While at it, also remove pre-3.0-migration hacks introduced for backward compatibility which ar

Re: [PATCH v3 12/14] ppc/spapr: remove deprecated machine pseries-2.12-sxxm

On 10/7/24 17:38, Harsh Prateek Bora wrote: Commit 0cac0f1b964 marked pseries-2.12 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.12-sxxm specific code with this patch. Suggested-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora --- hw/ppc/spapr.c |

Re: [PATCH v3 14/14] ppc/spapr: remove deprecated machine pseries-3.0

On 10/7/24 17:38, Harsh Prateek Bora wrote: As per Qemu's deprecation policy [1], and the mailing list discussion that happened on [2], pseries-3.0 is more than 6 years old since release and therefore due for deletion as already deprecated for >3 years. [1] https://www.qemu.org/docs/master/about

Re: [PATCH] net: Check if nc is NULL in qemu_get_vnet_hdr_len()

On Sat, Aug 17, 2024 at 04:00:43PM +0900, Akihiko Odaki wrote: > A netdev may not have a peer specified, resulting in NULL. We should > make it behave like /dev/null in such a case instead of letting it > cause segmentatin fault. segmentation > > Fixes: 4b52d63249a5 ("tap: Remove qemu_using_vnet

[PATCH] sched_attr: Do not define for glibc >= 2.41

glibc 2.41+ has added [1] definitions for sched_setattr and sched_getattr functions and struct sched_attr. Therefore, it needs to be checked for here as well before defining sched_attr Fixes builds with glibc/trunk [1] https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=21571ca0d70302909cf72

[PATCH v6] hw/misc/aspeed_hace: Fix SG Accumulative hashing

From: Alejandro Zeise Make the Aspeed HACE module use the new qcrypto accumulative hashing functions when in scatter-gather accumulative mode. A hash context will maintain a "running-hash" as each scatter-gather chunk is received. Previously each scatter-gather "chunk" was cached so the hash cou

Re: [PATCH v2 1/1] x86: Add support save/load HWCR MSR

On Wed, Oct 09, 2024 at 05:51:09PM +0800, Gao Shiyuan wrote: > Date: Wed, 9 Oct 2024 17:51:09 +0800 > From: Gao Shiyuan > Subject: [PATCH v2 1/1] x86: Add support save/load HWCR MSR > X-Mailer: git-send-email 2.39.3 (Apple Git-146) > > KVM commit 191c8137a939 ("x86/kvm: Implement HWCR support") >

Re: [PATCH] target/i386: Add more features enumerated by CPUID.7.2.EDX

On Thu, Oct 10, 2024 at 03:17:16PM +0200, Paolo Bonzini wrote: > Date: Thu, 10 Oct 2024 15:17:16 +0200 > From: Paolo Bonzini > Subject: Re: [PATCH] target/i386: Add more features enumerated by > CPUID.7.2.EDX > > On 10/9/24 10:12, Chao Gao wrote: > > > > diff --git a/target/i386/cpu.c b/target/i

Re: [PATCH v1 5/7] target/riscv: Enable 32-bit only registers for RV64 with sxl32

On Mon, Oct 7, 2024 at 1:52 PM LIU Zhiwei wrote: > > From: TANG Tiancheng > > Allow reading 32-bit only registers like timeh and stimecmph when > booting a 32-bit Linux kernel on RV64 when sxl32 is true. > > Signed-off-by: TANG Tiancheng > --- > target/riscv/csr.c | 4 ++-- > 1 file changed, 2

Re: [PATCH v1 3/7] target/riscv: Read pte and satp based on SXL in PTW

On Mon, Oct 7, 2024 at 1:36 PM LIU Zhiwei wrote: > > From: TANG Tiancheng > > Satp and PTE are always SXLEN-bit. when SXLEN is 32, > read PTE as 4 bytes, and treat satp as SATP32. > > Signed-off-by: TANG Tiancheng Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu_helper.c | 4

Re: [PATCH v1 2/7] target/riscv: Fix satp read and write implicitly or explicitly.

On Mon, Oct 7, 2024 at 1:35 PM LIU Zhiwei wrote: > > From: TANG Tiancheng > > CSR satp is SXLEN bits in length and always has the $layout determined by > the SXL configuration, regardless of the current XLEN. > > Only process CSR satp, as we still don't have a riscv_cpu_vsxl API > currently. > >

Re: [PATCH v1 7/7] target/riscv: Expose sxl32 configuration in RISC-V CPU

On Mon, Oct 7, 2024 at 2:19 PM LIU Zhiwei wrote: > > From: TANG Tiancheng > > Enable with "-cpu rv64,sxl32=on". > When sxl32 is enabled, RV64 can boot 32-bit Linux with > 64-bit Opensbi while requiring to make minor modifications > to the Linux kernel source code. > > How to patch linux: > https:

Re: [PATCH v1 0/7] target/riscv: Support SXL32 on RV64 CPU

On Mon, Oct 7, 2024 at 1:35 PM LIU Zhiwei wrote: > > From: TANG Tiancheng > > We have implemented UXL32 on QEMU already. It enables us to run RV32 > applications on RV64 Linux on QEMU. Similarly, RISCV specification > doesn't limit the SXLEN to be the same with MXLEN. In this patch set, > we will

Re: [PATCH v1 1/7] target/riscv: Fix sstatus read and write

On Mon, Oct 7, 2024 at 1:35 PM LIU Zhiwei wrote: > > From: TANG Tiancheng > > Sstatus is SXLEN bits in length and always has the layout determined by > the SXL configuration, regardless of the current XLEN. > > Signed-off-by: TANG Tiancheng > Fixes: b550f89457 (target/riscv: Compute mstatus.sd o

Re: [PATCH v2 5/8] target/riscv: Add Smdbltrp CSRs handling

On Wed, Sep 25, 2024 at 10:02 PM Clément Léger wrote: > > Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior. > > Signed-off-by: Clément Léger > --- > target/riscv/cpu_bits.h | 1 + > target/riscv/cpu_cfg.h | 1 + > target/riscv/csr.c | 15 +++ > 3 files c

Re: [PATCH v2 4/8] target/riscv: Add Ssdbltrp ISA extension enable switch

On Wed, Sep 25, 2024 at 9:59 PM Clément Léger wrote: > > Add the switch to enable the Ssdbltrp ISA extension. > > Signed-off-by: Clément Léger > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 65347ccd5a..4f52cf7

Re: [PATCH v2 3/8] target/riscv: Implement Ssdbltrp exception handling

On Wed, Sep 25, 2024 at 9:59 PM Clément Léger wrote: > > When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode > while SSTATUS.SDT isn't cleared, generate a double trap exception to > M-mode. > > Signed-off-by: Clément Léger > --- > target/riscv/cpu.c| 2 +- > target/r

[PATCH v2 3/4] Avoiding freeing line prematurely. It's now only freed at the end of the function.

Signed-off-by: Dehan Meng --- qga/commands-linux.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/qga/commands-linux.c b/qga/commands-linux.c index b905f33a57..4f0e38be81 100644 --- a/qga/commands-linux.c +++ b/qga/commands-linux.c @@ -2137,8 +2137,7 @@ GuestNetworkRout

[PATCH v2 4/4] For correcting code style: Variable declarations moved to the beginning of blocks Followed the coding style of using snake_case for variable names. And merged redundant route and networ

Signed-off-by: Dehan Meng --- qga/commands-linux.c | 116 --- 1 file changed, 53 insertions(+), 63 deletions(-) diff --git a/qga/commands-linux.c b/qga/commands-linux.c index 4f0e38be81..c6cca630ef 100644 --- a/qga/commands-linux.c +++ b/qga/commands-linux

[PATCH v2 1/4] sscanf return values are checked to ensure correct parsing.

Signed-off-by: Dehan Meng --- qga/commands-linux.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qga/commands-linux.c b/qga/commands-linux.c index 51d5e3d927..2c2b5f4ff2 100644 --- a/qga/commands-linux.c +++ b/qga/commands-linux.c @@ -2103,7 +2103,9 @@ static char *hexToI

[PATCH v2 2/4] Proper initialization of n to 0 for getline to function correctly.

Signed-off-by: Dehan Meng --- qga/commands-linux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qga/commands-linux.c b/qga/commands-linux.c index 2c2b5f4ff2..b905f33a57 100644 --- a/qga/commands-linux.c +++ b/qga/commands-linux.c @@ -2126,7 +2126,7 @@ GuestNetworkRouteList

[PATCH v2 0/4] qemu-ga: Fix some potential issues find by coverity

v2: Split v1 up to separate commits for each logically independent change Dehan Meng (4): sscanf return values are checked to ensure correct parsing. Proper initialization of n to 0 for getline to function correctly. Avoiding freeing line prematurely. It's now only freed at the end of th

Re: [PATCH v2 2/8] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior

On Wed, Sep 25, 2024 at 9:58 PM Clément Léger wrote: > > When the Ssdbltrp extension is enabled, SSTATUS.SDT field is cleared > when executing sret. When executing mret/mnret, SSTATUS.SDT is cleared > when returning to U, VS or VU and VSSTATUS.SDT is cleared when returning > to VU from HS. I don'

Re: [PATCH v2 1/8] target/riscv: Add Ssdbltrp CSRs handling

On Wed, Sep 25, 2024 at 10:02 PM Clément Léger wrote: > > Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT, > {H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the > presence of the Ssdbltrp ISA extension. > > Signed-off-by: Clément Léger Reviewed-by: Alistair Francis

Re: [PATCH 3/4] target/riscv/kvm: add kvm-aia bools props

On Tue, Sep 24, 2024 at 10:46 PM Daniel Henrique Barboza wrote: > > Boolean properties are preferrable in comparision to string properties > since they don't require a string parsing. > > Add three bools that represents the available kvm-aia mode: > riscv-aia-emul, riscv-aia-hwaccel, riscv-aia-aut

Re: [PATCH 2/4] target/riscv/kvm: clarify how 'riscv-aia' default works

On Tue, Sep 24, 2024 at 10:46 PM Daniel Henrique Barboza wrote: > > We do not have control in the default 'riscv-aia' default value. We can > try to set it to a specific value, in this case 'auto', but there's no > guarantee that the host will accept it. > > Couple with this we're always doing a '

Re: [PATCH 1/4] target/riscv/kvm: set 'aia_mode' to default in error path

On Tue, Sep 24, 2024 at 10:46 PM Daniel Henrique Barboza wrote: > > When failing to set the selected AIA mode, 'aia_mode' is left untouched. > This means that 'aia_mode' will not reflect the actual AIA mode, > retrieved in 'default_aia_mode', > > This is benign for now, but it will impact QMP quer

Re: [PATCH -qemu] hw/cxl: Support get/set mctp response payload size

On Wed, Oct 09, 2024 at 06:41:57PM -0700, Davidlohr Bueso wrote: > Add Get/Set Response Message Limit commands. > > Signed-off-by: Davidlohr Bueso The commit log may include the cxl spec reference. Otherwise, Reviewed-by: Fan Ni > --- > hw/cxl/cxl-mailbox-utils.c | 68 ++

[PATCH v2 13/16] target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl()

Directly use tcg_constant_tl() for constant integer, this save a call to tcg_gen_movi_tl(), often saving a temp register. Most of the places found using the following Coccinelle spatch script: @@ identifier tmp; constant val; @@ *TCGv tmp = tcg_temp_new(); ... *tcg_gen_

[PATCH v2 10/16] target/mips: Replace MO_TE by mo_endian()

Replace compile-time MO_TE evaluation by runtime mo_endian() one, which expand target endianness from DisasContext. Mechanical change using: $ sed -i -e 's/MO_TE/mo_endian(ctx)/' \ $(git grep -l MO_TE target/mips) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by:

[PATCH v2 04/16] target/mips: Replace MO_TE by mo_endian_env() in get_pte()

Replace compile-time MO_TE evaluation by runtime mo_endian_env() one, which expand target endianness from vCPU env. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/tcg/sysemu/tlb_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-

[PATCH v2 16/16] hw/mips: Have mips_cpu_create_with_clock() take an endianness argument

mips_cpu_create_with_clock() creates a vCPU. Pass it the vCPU endianness requested by argument. Update the board call sites. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/cpu.h| 4 +++- hw/mips/fuloong2e.c | 2 +- hw/mips/jaz

[PATCH v2 05/16] target/mips: Convert mips16e decr_and_load/store() macros to functions

Functions are easier to rework than macros. Besides, there is no gain here in inlining these. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Reviewed-by: Richard Henderson --- target/mips/tcg/mips16e_translate.c.inc | 101 +--- 1 file

[PATCH v2 11/16] target/mips: Have gen_addiupc() expand $pc during translation

Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 4802a6a1d87..41f25c938de 100644 --- a/target/mips/t

[PATCH v2 15/16] hw/mips/cps: Set the vCPU 'cpu-big-endian' property

Have the CPS expose a 'cpu-big-endian' property so it can set it to the vCPUs it creates. Note, since the number of vCPUs created is dynamic, we can not use QOM aliases. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- include/hw/mips/cps.h | 1 + hw/mi

[PATCH v2 12/16] target/mips: Use gen_op_addr_addi() when possible

Replace tcg_gen_movi_tl() + gen_op_addr_add() by a single gen_op_addr_addi() call. gen_op_addr_addi() calls tcg_gen_addi_tl() which might optimize if the immediate is zero. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 1

[PATCH v2 14/16] target/mips: Expose MIPSCPU::is_big_endian property

Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/cpu.h | 3 +++ target/mips/cpu.c | 12 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/targ

[PATCH v2 08/16] target/mips: Rename unused sysemu argument of OP_LD_ATOMIC()

In commit 6d0cad12594 ("target/mips: Finish conversion to tcg_gen_qemu_{ld,st}_*") we renamed the argument of the user definition. Rename the system part for coherency. Since the argument is ignored, prefix with 'ignored_'. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.c |

[PATCH v2 09/16] target/mips: Introduce mo_endian() helper

Introduce mo_endian() which returns the endian MemOp corresponding to the vCPU DisasContext. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/tcg/translate.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/mips/tcg/translate.

[PATCH v2 07/16] target/mips: Explode MO_TExx -> MO_TE | MO_xx

Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/mips); \ done manually remove superfluous

[PATCH v2 02/16] target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian()

Methods using the 'cpu_' prefix usually take a (Arch)CPUState argument. Since this method takes a DisasContext argument, rename it as disas_is_bigendian(). Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 2 +- target/mips/tcg/

[PATCH v2 06/16] target/mips: Factor mo_endian_rev() out of MXU code

Instead of swapping the reversed target endianness using MO_BSWAP, directly return the correct endianness. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 5 + target/mips/tcg/mxu_translate.c | 8 2 files changed, 9 insert

[PATCH v2 01/16] target/mips: Declare mips_env_is_bigendian() in 'internal.h'

In order to re-use cpu_is_bigendian(), declare it on "internal.h" after renaming it as mips_env_is_bigendian(). Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20241004162118.84570-6-phi...@linaro.org> --- target/mips/internal.h| 5 ++

[PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge

Since v1: - Addressed rth review comment (adding new patches) Get vCPU endianness from CP0::BE bit. Propagate endianness at the board level, using QOM property. Remove target-specific endianness knowledge from target/. Philippe Mathieu-Daudé (16): target/mips: Declare mips_env_is_bigendian() in

[PATCH v2 03/16] target/mips: Introduce mo_endian_env() helper

Introduce mo_endian_env() which returns the endian MemOp corresponding to the vCPU env. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/internal.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/mips/internal.h b/target/mips

Re: precreate phase

On Thu, Oct 10, 2024 at 11:19:15PM +0200, Paolo Bonzini wrote: > Moving migration_object_init() earlier sounds like a good idea anyway! I take the last sentence back of my other reply - I believe I underestimated the potential reviewers of the upcoming precreate patchset.. :) -- Peter Xu

Re: [PATCH V2 13/13] migration: cpr-transfer mode

On Thu, Oct 10, 2024 at 04:06:13PM -0400, Steven Sistare wrote: > vhost requires us to stop the vm early: > qmp_migrate > stop vm > migration_call_notifiers MIG_EVENT_PRECOPY_CPR_SETUP > vhost_cpr_notifier > vhost_reset_device - must be after stop vm >

Re: precreate phase

On 10/10/24 22:07, Steven Sistare wrote: Peter, Fabiano, I have a nice solution that allows dest qemu configuration with cpr- transfer. I define a new qemu initialization phase called 'precreate' which occurs before most backends or devices have been created.  The only exception is monitor dev

Re: precreate phase

On Thu, Oct 10, 2024 at 05:51:16PM -0300, Fabiano Rosas wrote: > Steven Sistare writes: > > > Peter, Fabiano, > > > > I have a nice solution that allows dest qemu configuration with > > cpr-transfer. > > I define a new qemu initialization phase called 'precreate' which occurs > > before most bac

Re: precreate phase

Steven Sistare writes: > Peter, Fabiano, > > I have a nice solution that allows dest qemu configuration with cpr-transfer. > I define a new qemu initialization phase called 'precreate' which occurs > before most backends or devices have been created. The only exception > is monitor devices and t

Re: [RFC RESEND 0/6] hugetlbfs largepage RAS project

On 10/9/24 17:45, Peter Xu wrote: On Thu, Sep 19, 2024 at 06:52:37PM +0200, William Roche wrote: Hello David, I hope my last week email answered your interrogations about:     - retrieving the valid data from the lost hugepage     - the need of smaller pages to replace a failed large page   

Re: [PATCH 11/12] target/mips: Remove target-specific code in mips_cpu_reset_hold()

On 3/10/24 20:01, Richard Henderson wrote: On 9/30/24 02:11, Philippe Mathieu-Daudé wrote: Since all code creating vCPUs now set the 'cpu-big-endian' property, we can remove the target-specific #ifdef'ry in mips_cpu_reset_hold(): the CP0C0_BE bit is set using the property cpu->is_big_endian valu

precreate phase

Peter, Fabiano, I have a nice solution that allows dest qemu configuration with cpr-transfer. I define a new qemu initialization phase called 'precreate' which occurs before most backends or devices have been created. The only exception is monitor devices and the qtest device and their chardevs,

Re: [PATCH V2 13/13] migration: cpr-transfer mode

On 10/9/2024 4:36 PM, Peter Xu wrote: On Wed, Oct 09, 2024 at 04:09:45PM -0400, Steven Sistare wrote: On 10/9/2024 3:06 PM, Peter Xu wrote: On Wed, Oct 09, 2024 at 02:43:44PM -0400, Steven Sistare wrote: On 10/8/2024 3:48 PM, Peter Xu wrote: On Tue, Oct 08, 2024 at 04:11:38PM -0300, Fabiano R

Re: [PATCH V2 13/13] migration: cpr-transfer mode

On 10/9/2024 6:08 PM, Fabiano Rosas wrote: Peter Xu writes: On Wed, Oct 09, 2024 at 04:18:31PM -0400, Steven Sistare wrote: Yes, I am also brainstorming along these lines, looking for more gotcha's, but its a big design change. I don't love it so far. These issues all creep in because of tra

Re: [PATCH 0/7] migration: query-migrationthreads enhancements and cleanups

On Wed, Oct 02, 2024 at 07:58:48AM +0200, Markus Armbruster wrote: > Peter Xu writes: > > > On Tue, Oct 01, 2024 at 03:25:14PM +0100, Daniel P. Berrangé wrote: > >> On Tue, Oct 01, 2024 at 07:46:09AM +0200, Markus Armbruster wrote: > >> > Command query-migrationthreads went in without a QAPI ACK.

Re: [PATCH 18/23] accel/tcg: Call cpu_ld*_code_mmu from cpu_ld*_code

On 10/9/24 17:23, Pierrick Bouvier wrote: On 10/9/24 08:08, Richard Henderson wrote: Ensure a common entry point for all code lookups. Signed-off-by: Richard Henderson ---   accel/tcg/cputlb.c | 8   1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/accel/tcg/cputlb.c b/acc

Re: [PATCH 14/23] accel/tcg: Replace victim_tlb_hit with tlbtree_hit

On 10/9/24 17:10, Pierrick Bouvier wrote: +static bool tlbtree_hit(CPUState *cpu, int mmu_idx, +    MMUAccessType access_type, vaddr addr)   { -    size_t vidx; +    CPUTLBDesc *desc = &cpu->neg.tlb.d[mmu_idx]; +    CPUTLBDescFast *fast = &cpu->neg.tlb.f[mmu_idx]; +    CPUTLBE

Re: [PATCH v2 5/7] target/i386/cpu: Improve errors for out of bounds property values

Philippe Mathieu-Daudé writes: > On 10/10/24 12:01, Markus Armbruster wrote: >> The error message for a "stepping" value that is out of bounds is a >> bit odd: >> $ qemu-system-x86_64 -cpu qemu64,stepping=16 >> qemu-system-x86_64: can't apply global qemu64-x86_64-cpu.stepping=16: >> Pr

Re: [Bug Report][RFC PATCH 1/1] block: fix failing assert on paused VM migration

Vladimir Sementsov-Ogievskiy writes: > On 10.10.24 17:30, Fabiano Rosas wrote: >> Vladimir Sementsov-Ogievskiy writes: >> >>> On 09.10.24 23:53, Fabiano Rosas wrote: Vladimir Sementsov-Ogievskiy writes: > On 30.09.24 17:07, Andrey Drobyshev wrote: >> On 9/30/24 12:25 PM, Vlad

[PATCH 3/8] hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic()

Similar to the riscv_is_kvm_aia_aplic_imsic() helper from riscv_aplic.c, the existing virt_use_kvm_aia() is testing for KVM aia=aplic-imsic with in-kernel irqchip enabled. It is not checking for a generic AIA support. Rename the helper to virt_use_kvm_aia_aplic_imsic() to reflect what the helper i

[PATCH 8/8] docs: update riscv/virt.rst with kernel-irqchip=split support

Also add a new page, docs/specs/riscv-aia.rst, where we're documenting the state of AIA support in QEMU w.r.t the controllers being emulated or not depending on the AIA and accelerator settings. Signed-off-by: Daniel Henrique Barboza --- docs/specs/index.rst | 1 + docs/specs/riscv-aia.rs

[PATCH 1/8] hw/intc/riscv_aplic: rename is_kvm_aia()

The helper is_kvm_aia() is checking not only for AIA, but for aplic-imsic (i.e. "aia=aplic-imsic" in 'virt' RISC-V machine) with an in-kernel chip present. Rename it to be a bit clear what the helper is doing since we'll add more AIA helpers in the next patches. Make the helper public because the

[PATCH 0/8] riscv: AIA userspace irqchip_split support

Hi, This series adds AIA irqchip_split support, effective when using AIA with aia=aplic-imsic and -accel kvm,kernel-irqchip=split. The main difference between what we currently have and irqchip_split() mode is that, when using split mode, QEMU will emulate the APLIC controller instead of using t

[PATCH 4/8] target/riscv/kvm: consider irqchip_split() in aia_create()

Before adding support to kernel-irqchip=split when using KVM AIA we need to change how we create the in-kernel AIA device. In the use case we have so far, i.e. in-kernel irqchip without split mode, both the s-mode APLIC and IMSIC controllers are provided by the irqchip. In irqchip_split() mode we'

[PATCH 5/8] hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers

The current logic to determine if we don't need an emulated APLIC controller, i.e. KVM will provide for us, is to determine if we're running KVM, with in-kernel irqchip support, and running aia=aplic-imsic. This is modelled by riscv_is_kvm_aia_aplic_imsic() and virt_use_kvm_aia_aplic_imsic(). This

[PATCH 2/8] hw/riscv/virt.c: reduce virt_use_kvm_aia() usage

In create_fdt_sockets() we have the following pattern: if (kvm_enabled() && virt_use_kvm_aia(s)) { (... do stuff ...) } else { (... do other stuff ...) } if (kvm_enabled() && virt_use_kvm_aia(s)) { (... do more stuff ...) } else { (... do more ot

[PATCH 7/8] target/riscv/kvm: remove irqchip_split() restriction

Remove the 'irqchip_split()' restriction in kvm_arch_init() now that we have support for "-accel kvm,kernel-irqchip=split". Signed-off-by: Daniel Henrique Barboza --- target/riscv/kvm/kvm-cpu.c | 5 - 1 file changed, 5 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/

[PATCH 6/8] hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic

The last step to enable KVM AIA aplic-imsic with irqchip in split mode is to deal with how MSIs are going to be sent. In our current design we don't allow an APLIC controller to send MSIs unless it's on m-mode. And we also do not allow Supervisor MSI address configuration via the 'smsiaddrcfg' and

Re: [PATCH] migration: Cleanup migrate_fd_cleanup() on accessing to_dst_file

On Thu, Sep 19, 2024 at 12:30:42PM -0400, Peter Xu wrote: > The cleanup function can in many cases needs cleanup on its own. > > The major thing we want to do here is not referencing to_dst_file when > without the file mutex. When at it, touch things elsewhere too to make it > look slightly bette

Re: [PATCH 2/7] docs/devel/blkverify: Convert to rST format

On 16/08/2024 15.22, Peter Maydell wrote: Convert blkverify.txt to rST format. Signed-off-by: Peter Maydell --- MAINTAINERS | 1 + docs/devel/{blkverify.txt => blkverify.rst} | 30 - docs/devel/index-build.rst | 1 + Ma

Re: [PATCH 1/7] docs/devel/blkdebug: Convert to rST format

On 16/08/2024 15.22, Peter Maydell wrote: Convert blkdebug.txt to rST format. We put it into index-build.rst because it falls under the "test" part of "QEMU Build and Test System". Signed-off-by: Peter Maydell --- At least, index-build seemed the most plausible home to me... I recently split

Re: [PATCH v3 2/2] gdbstub/helpers: Introduce ldtul_$endian_p() helpers

Philippe Mathieu-Daudé writes: > Introduce ldtul_le_p() and ldtul_be_p() to use directly > in place of ldtul_p() when a target endianness is fixed. > > Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alex Bennée -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH 07/13] hw/xtensa/xtfpga: Remove TARGET_BIG_ENDIAN #ifdef'ry

On 3/10/24 18:35, Richard Henderson wrote: On 9/30/24 00:34, Philippe Mathieu-Daudé wrote: Move code evaluation from preprocessor to compiler so both if() ladders are processed. Mostly style change. Signed-off-by: Philippe Mathieu-Daudé ---   hw/xtensa/xtfpga.c | 12 +++-   1 file chang

Re: [PATCH v3 0/2] gdbstub: Introduce ldtul_$endian_p() helpers

On 10/10/24 10:52, Philippe Mathieu-Daudé wrote: Only unreviewed patches from v2: https://lore.kernel.org/qemu-devel/20241004163042.85922-1-phi...@linaro.org/ Philippe Mathieu-Daudé (2): exec/tswap: Massage target_needs_bswap() definition gdbstub/helpers: Introduce ldtul_$endian_p() helper

[PATCH v3 1/2] exec/tswap: Massage target_needs_bswap() definition

Invert target_needs_bswap() comparison to match the COMPILING_PER_TARGET definition (2 lines upper). Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20241004162118.84570-2-phi...@linaro.org> --- include/exec/tswap.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/e

[PATCH v3 2/2] gdbstub/helpers: Introduce ldtul_$endian_p() helpers

Introduce ldtul_le_p() and ldtul_be_p() to use directly in place of ldtul_p() when a target endianness is fixed. Signed-off-by: Philippe Mathieu-Daudé --- include/gdbstub/helpers.h | 4 1 file changed, 4 insertions(+) diff --git a/include/gdbstub/helpers.h b/include/gdbstub/helpers.h index

[PATCH v3 0/2] gdbstub: Introduce ldtul_$endian_p() helpers

Only unreviewed patches from v2: https://lore.kernel.org/qemu-devel/20241004163042.85922-1-phi...@linaro.org/ Philippe Mathieu-Daudé (2): exec/tswap: Massage target_needs_bswap() definition gdbstub/helpers: Introduce ldtul_$endian_p() helpers include/exec/tswap.h | 2 +- include/gdbstub

Re: [PATCH v2 7/7] qerror: QERR_PROPERTY_VALUE_OUT_OF_RANGE is no longer used, drop

On 10/10/24 12:01, Markus Armbruster wrote: Signed-off-by: Markus Armbruster --- include/qapi/qmp/qerror.h | 3 --- 1 file changed, 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v2 6/7] hw/intc/openpic: Improve errors for out of bounds property values

On 10/10/24 12:01, Markus Armbruster wrote: The error message doesn't matter much, as the "openpic" device isn't user-creatable. But it's the last use of QERR_PROPERTY_VALUE_OUT_OF_RANGE, which has to go. Change the message just like the previous commit did for x86 CPUs. Signed-off-by: Markus

[RFC PATCH] cli: add connect-gpios option

From: Valentin Ghita Add option to allow for connecting device GPIOs. This is useful when adding a peripheral device from the command line which uses an interrupt. It takes the following options: * in-dev-path, out-dev-path - required, the device canonical object path (e.g. /machine/periphera

Re: [PATCH v2 5/7] target/i386/cpu: Improve errors for out of bounds property values

On 10/10/24 12:01, Markus Armbruster wrote: The error message for a "stepping" value that is out of bounds is a bit odd: $ qemu-system-x86_64 -cpu qemu64,stepping=16 qemu-system-x86_64: can't apply global qemu64-x86_64-cpu.stepping=16: Property .stepping doesn't take value 16 (minimum

Re: [PATCH 0/7] error: Eliminate QERR_PROPERTY_VALUE_OUT_OF_RANGE

Daniel P. Berrangé writes: > On Thu, Oct 10, 2024 at 04:59:13PM +0200, Markus Armbruster wrote: >> Please ignore this one, wrong version, I'll resend. > > Unless I'm missing something subtle, your v2 was only commit message tweaks, > so feel free to apply my R-bs as is. Correct. Thanks!

[PATCH v2 7/7] qerror: QERR_PROPERTY_VALUE_OUT_OF_RANGE is no longer used, drop

Signed-off-by: Markus Armbruster --- include/qapi/qmp/qerror.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/qapi/qmp/qerror.h b/include/qapi/qmp/qerror.h index 101c1141b9..d1db6f18cd 100644 --- a/include/qapi/qmp/qerror.h +++ b/include/qapi/qmp/qerror.h @@ -23,7 +23,4 @@ #define

[PATCH v2 6/7] hw/intc/openpic: Improve errors for out of bounds property values

The error message doesn't matter much, as the "openpic" device isn't user-creatable. But it's the last use of QERR_PROPERTY_VALUE_OUT_OF_RANGE, which has to go. Change the message just like the previous commit did for x86 CPUs. Signed-off-by: Markus Armbruster --- hw/intc/openpic.c | 5 +

[PATCH v2 5/7] target/i386/cpu: Improve errors for out of bounds property values

The error message for a "stepping" value that is out of bounds is a bit odd: $ qemu-system-x86_64 -cpu qemu64,stepping=16 qemu-system-x86_64: can't apply global qemu64-x86_64-cpu.stepping=16: Property .stepping doesn't take value 16 (minimum: 0, maximum: 15) The "can't apply global" part

Re: [PULL 16/17] crypto: drop obsolete back compat logic for old nettle

On 10/10/24 13:20, Daniel P. Berrangé wrote: The nettle 2.x series declared all the hash functions with 'int' for the data size. Since we dropped support for anything older than 3.4 we can assume nettle is using 'size_t' and thus avoid the back compat looping logic. Reviewed-by: Cédric Le Goater

Re: [PATCH v2 3/7] block: Adjust check_block_size() signature

On 10/10/24 12:01, Markus Armbruster wrote: Parameter @id is no longer used, drop. Return a bool to indicate success / failure, as recommended by qapi/error.h. Signed-off-by: Markus Armbruster --- util/block-helpers.h | 3 +-- block/export/vduse-blk.c | 7 ++---

Re: [PATCH] net: Check if nc is NULL in qemu_get_vnet_hdr_len()

On Sat, 17 Aug 2024 16:00:43 +0900 Akihiko Odaki wrote: > A netdev may not have a peer specified, resulting in NULL. We should > make it behave like /dev/null in such a case instead of letting it > cause segmentatin fault. > > Fixes: 4b52d63249a5 ("tap: Remove qemu_using_vnet_hdr()") > Reported-

[PULL 11/17] crypto/hash-gcrypt: Remove old hash API functions

From: Alejandro Zeise Removes old hash implementation in the gcrypt hash driver. Signed-off-by: Alejandro Zeise Reviewed-by: Daniel P. Berrangé [ clg: - Fixed spelling in commit log ] Signed-off-by: Cédric Le Goater Reviewed-by: Daniel P. Berrangé Signed-off-by: Daniel P. Berrangé --- cryp

[PULL 09/17] tests/unit/test-crypto-hash: accumulative hashing

From: Alejandro Zeise Added an accumulative hashing test. Checks for functionality of the new hash create, update, finalize and free functions. Signed-off-by: Alejandro Zeise [ clg: - Improved test_hash_accumulate() with g_autofree variables ] Signed-off-by: Cédric Le Goater Reviewed-by: Danie

[PULL 14/17] crypto/hash-afalg: Remove old hash API functions

From: Alejandro Zeise Removes the old hash API functions in the afalg driver, and modifies the hmac function to use the new helper functions. Signed-off-by: Alejandro Zeise Reviewed-by: Daniel P. Berrangé [ clg: - Checkpatch fixes ] Signed-off-by: Cédric Le Goater Reviewed-by: Daniel P. Berra

[PULL 06/17] util/iov: Introduce iov_send_recv_with_flags()

From: Alejandro Zeise In order to support a new update function, a flag needs to be passed to the kernel via the socket send call (MSG_MORE) to notify it that more data is to be expected to calculate the hash correctly. Add a new iov helper for this purpose. Signed-off-by: Alejandro Zeise [ cl

[PULL 08/17] crypto/hash: Implement and use new hash API

From: Alejandro Zeise Changes the public hash API implementation to support accumulative hashing. Implementations for the public functions are added to call the new driver functions that implement context creation, updating, finalization, and destruction. Additionally changes the "shortcut" fun

[PULL 16/17] crypto: drop obsolete back compat logic for old nettle

The nettle 2.x series declared all the hash functions with 'int' for the data size. Since we dropped support for anything older than 3.4 we can assume nettle is using 'size_t' and thus avoid the back compat looping logic. Reviewed-by: Cédric Le Goater Signed-off-by: Daniel P. Berrangé --- crypt

[PULL 15/17] crypto/hashpriv: Remove old hash API function

From: Alejandro Zeise Remove old hash_bytesv function, as it was replaced by the 4 new functions. Signed-off-by: Alejandro Zeise Reviewed-by: Daniel P. Berrangé Signed-off-by: Daniel P. Berrangé --- crypto/hashpriv.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/crypto/hashpriv.h

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