Re: [PATCH] migration: Refine the convergence detection

On Wed, Aug 7, 2024 at 12:45 AM Peter Xu wrote: > On Mon, Aug 05, 2024 at 03:03:27PM +0800, Yong Huang wrote: > > Sorry for the late reply. > > > > On Wed, Jul 31, 2024 at 4:01 AM Peter Xu wrote: > > > > > On Wed, Jul 24, 2024 at 07:39:29PM +0800, Hyman Huang wrote: > > > > Currently, the conver

Re: [PATCH 0/2] target/i386: Fix carry flag for BLSI

On 8/1/24 17:58, Richard Henderson wrote: Fix #2175. r~ Richard Henderson (2): target/i386: Split out gen_prepare_val_nz target/i386: Fix carry flag for BLSI target/i386/cpu.h| 5 + target/i386/tcg/cc_helper.c | 18 target/i3

RE: [PATCH v3 0/2] RISC-V: Add preliminary textra trigger CSR functions

Hello Alistair, > -Original Message- > From: Alistair Francis > Sent: Wednesday, July 24, 2024 10:40 AM > To: Alvin Che-Chia Chang(張哲嘉) > Cc: qemu-ri...@nongnu.org; qemu-devel@nongnu.org; > alistair.fran...@wdc.com; bin.m...@windriver.com; liwei1...@gmail.com; > dbarb...@ventanamicro.com

Re: [RFC PATCH-for-9.1? 1/2] target/arm: Move qmp_query_gic_capabilities() to hw/intc/

Philippe Mathieu-Daudé writes: > qmp_query_gic_capabilities() is not specific to the ARM > architecture but to the GIC device which is modelled in > hw/intc/, so move the code there for clarity. No logical > change intended. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/intc/arm_gic_qmp.

Re: [PATCH 1/2] include: bitops: Add mask extract64/deposit64

On Tue, Aug 6, 2024 at 5:32 PM Richard Henderson wrote: > > On 8/5/24 14:33, Alistair Francis wrote: > > Based on the RISC-V get_field() and set_field() macros add > > mask_extract64() and mask_deposit64() bitop functions. These can extrac > > and deposit values into fields using a bit field mask

[PATCH for-9.1] tcg/ppc: Sync tcg_out_test and constraints

Ensure the code structure is the same for matching constraints and emitting code, lest we allow constants that cannot be trivially tested. Cc: qemu-sta...@nongnu.org Fixes: ad788aebbab ("tcg/ppc: Support TCG_COND_TST{EQ,NE}") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2487 Signed-off-

Re: [PATCH v6] virtio-pci: Fix the use of an uninitialized irqfd

On Tue, Aug 6, 2024 at 5:37 PM Cindy Lu wrote: > > The crash was reported in MAC OS and NixOS, here is the link for this bug > https://gitlab.com/qemu-project/qemu/-/issues/2334 > https://gitlab.com/qemu-project/qemu/-/issues/2321 > > In this bug, they are using the virtio_input device. The guest

Re: [RFC PATCH-for-9.1? 2/2] hw/intc/arm_gic: Only provide query-gic-capabilities when GIC built-in

On 8/7/24 00:19, Philippe Mathieu-Daudé wrote: When configuring QEMU with --without-default-devices and not including machines using a GIC, the GIC model is not built in but the 'query-gic-capabilities' command still returns false hopes about GIC: {"execute": "query-gic-capabilities"} {"re

Re: [RFC PATCH-for-9.1? 1/2] target/arm: Move qmp_query_gic_capabilities() to hw/intc/

On 8/7/24 00:19, Philippe Mathieu-Daudé wrote: qmp_query_gic_capabilities() is not specific to the ARM architecture but to the GIC device which is modelled in hw/intc/, so move the code there for clarity. But the GIC is certainly arm architecture specific. It's built into the CPU, and shares st

Re: [PATCH v3 20/20] linux-user: Add RISC-V zicfilp support in VDSO

On 8/7/24 10:06, Deepak Gupta wrote: Add zicfilp support in VDSO. VDSO functions need lpad instruction so that userspace could call this function when landing pad extension is enabled. This solution only works when toolchain always use landing pad label 1. Well, no, the lpad insns *could* use i

Re: [PATCH v3 19/20] linux-user: permit RISC-V CFI dynamic entry in VDSO

On 8/7/24 10:06, Deepak Gupta wrote: RISC-V CFI use new processor-specific dynamic entry in ELF. Permit it in VDSO post-processing script. Signed-off-by: Jim Shu Signed-off-by: Deepak Gupta --- linux-user/gen-vdso-elfn.c.inc | 7 +++ 1 file changed, 7 insertions(+) diff --git a/linux-u

Re: [PATCH v3 18/20] target/riscv: add trace-hooks for each case of sw-check exception

On 8/7/24 10:06, Deepak Gupta wrote: Violations to control flow rules setup by zicfilp and zicfiss lead to software check exceptions. To debug and fix such sw check issues in guest , add trace-hooks for each case. Signed-off-by: Jim Shu Signed-off-by: Deepak Gupta --- target/riscv/insn_trans

Re: [PATCH v3 16/20] disas/riscv: enable disassembly for zicfiss instructions

On 8/7/24 10:06, Deepak Gupta wrote: +/* if zicfiss enabled and mop5 is shadow stack */ +if (dec->cfg->ext_zicfiss && +((imm_mop5 & 0b11100) == 0b11100)) { +/* rs1=0 means ssrdp */ +

Re: [PATCH v3 14/20] target/riscv: mmu changes for zicfiss shadow stack protection

On 8/7/24 10:06, Deepak Gupta wrote: @@ -1105,15 +1119,45 @@ restart: return TRANSLATE_FAIL; } +/* + * When backward CFI is enabled, the R=0, W=1, X=0 reserved encoding + * is used to mark Shadow Stack (SS) pages. If back CFI enabled, allow + * normal loads on

Re: [PATCH v3 12/20] target/riscv: implement zicfiss instructions

On 8/7/24 12:39, Richard Henderson wrote: +static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk *a) +{ +    /* default for qemu-user, use regular RW memory and thus mmu_idx=0 */ +    int ss_mmu_idx = 0; This can't be right, since 0 is M_MODE. I'm wrong about m-mode here, but "0" is cert

Re: [PATCH v3 15/20] target/riscv: shadow stack mmu index for shadow stack instructions

On 8/7/24 10:06, Deepak Gupta wrote: Shadow stack instructions shadow stack mmu index for load/stores. `MMU_IDX_SS_ACCESS` at bit positon 3 is used as shadow stack index. Shadow stack mmu index depend on privilege and SUM bit. If shadow stack accesses happening in user mode, shadow stack mmu inde

Re: [PATCH v3 13/20] target/riscv: compressed encodings for sspush and sspopchk

On 8/7/24 10:06, Deepak Gupta wrote: sspush/sspopchk have compressed encodings carved out of zcmops. compressed sspush is designated as c.mop.1 while compressed sspopchk is designated as c.mop.5. Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly c.sspopchk x5 exists while c.sspop

Re: [PATCH v3 12/20] target/riscv: implement zicfiss instructions

On 8/7/24 10:06, Deepak Gupta wrote: zicfiss has following instructions - sspopchk: pops a value from shadow stack and compares with x1/x5. If they dont match, reports a sw check exception with tval = 3. - sspush: pushes value in x1/x5 on shadow stack - ssrdp: reads current shadow stack

Re: [PATCH 1/3] virtio_net: Add the check for vdpa's mac address

On Tue, Aug 6, 2024 at 5:44 PM Cindy Lu wrote: > > On Tue, 6 Aug 2024 at 11:07, Jason Wang wrote: > > > > On Tue, Aug 6, 2024 at 8:58 AM Cindy Lu wrote: > > > > > > When using a VDPA device, it is important to ensure that > > > the MAC address in the hardware matches the MAC address > > > from t

Re: [PATCH v3 11/20] target/riscv: tb flag for shadow stack instructions

On 8/7/24 10:06, Deepak Gupta wrote: Shadow stack instructions can be decoded as zimop / zcmop or shadow stack instructions depending on whether shadow stack are enabled at current privilege. This requires a TB flag so that correct TB generation and correct TB lookup happens. `DisasContext` gets

Re: [PATCH v3 10/20] target/riscv: introduce ssp and enabling controls for zicfiss

On 8/7/24 12:11, Richard Henderson wrote: On 8/7/24 10:06, Deepak Gupta wrote: diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a5a969a377..d72d6289fb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -185,6 +185,47 @@ static RISCVException zcmt(CPURISCVState *env, int csrno)

Re: [PATCH v3 10/20] target/riscv: introduce ssp and enabling controls for zicfiss

On 8/7/24 10:06, Deepak Gupta wrote: diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a5a969a377..d72d6289fb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -185,6 +185,47 @@ static RISCVException zcmt(CPURISCVState *env, int csrno) return RISCV_EXCP_NONE; } +stat

Re: [PATCH 2/2] tests/migration: Introduce multifd compression into guestperf

On Wed, Aug 7, 2024 at 3:22 AM Fabiano Rosas wrote: > yong.hu...@smartx.com writes: > > > From: Hyman Huang > > > > Guestperf tool does not cover the multifd compression option > > currently, it is worth supporting so that developers can > > analysis the migration performance with different > >

Re: [PATCH v3 08/20] disas/riscv: enabled `lpad` disassembly

On 8/7/24 10:06, Deepak Gupta wrote: Signed-off-by: Deepak Gupta Co-developed-by: Jim Shu Co-developed-by: Andy Chiu --- disas/riscv.c | 18 +- disas/riscv.h | 2 ++ 2 files changed, 19 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v3 07/20] target/riscv: zicfilp `lpad` impl and branch tracking

On 8/7/24 10:06, Deepak Gupta wrote: +++ b/target/riscv/insn32.decode @@ -40,6 +40,7 @@ %imm_z6 26:1 15:5 %imm_mop5 30:1 26:2 20:2 %imm_mop3 30:1 26:2 +%imm_cfi20 12:20 # Argument sets: &empty @@ -123,7 +124,10 @@ sfence_vm 000100000100 . 000 0 1110011 @sfence_vm

Re: [PATCH v2 13/13] target/riscv: Enable PMU related extensions to preferred rule

On Wed, Aug 7, 2024 at 2:06 AM Daniel Henrique Barboza wrote: > > > > On 8/6/24 5:46 AM, Andrew Jones wrote: > > On Tue, Jul 23, 2024 at 04:30:10PM GMT, Atish Patra wrote: > >> Counter delegation/configuration extension requires the following > >> extensions to be enabled. > >> > >> 1. Smcdeleg -

Re: [PATCH v3 07/20] target/riscv: zicfilp `lpad` impl and branch tracking

On 8/7/24 10:06, Deepak Gupta wrote: diff --git a/target/riscv/cpu_user.h b/target/riscv/cpu_user.h index 02afad608b..e6927ff847 100644 --- a/target/riscv/cpu_user.h +++ b/target/riscv/cpu_user.h @@ -15,5 +15,6 @@ #define xA6 16 #define xA7 17 /* syscall number for RVI ABI */ #define xT0 5

Re: [PATCH v3 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp

On 8/7/24 10:06, Deepak Gupta wrote: diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 364f3ee212..c7af430f38 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -134,6 +134,19 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags

Re: [PATCH v3 05/20] target/riscv: additional code information for sw check

On 8/7/24 10:06, Deepak Gupta wrote: sw check exception support was recently added. This patch further augments sw check exception by providing support for additional code which is provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever sw check exception is raised *tval gets the

Re: [PATCH v3 04/20] target/riscv: save and restore elp state on priv transitions

On 8/7/24 10:06, Deepak Gupta wrote: elp state is recorded in *status on trap entry (less privilege to higher privilege) and restored in elp from *status on trap exit (higher to less privilege). Additionally this patch introduces a forward cfi helper function to determine if current privilege ha

Re: [PATCH v3 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp

On 8/7/24 10:06, Deepak Gupta wrote: +/* enum for branch tracking state in cpu/hart */ +typedef enum { +NO_LP_EXPECTED = 0, +LP_EXPECTED = 1, +} cfi_elp; I know this is language is in the spec, but would it make more sense to use bool elp_expected; ? If not, Coding Style requires C

Re: [PATCH v3 01/20] accel/tcg: restrict assert on icount_enabled to qemu-system

On 8/7/24 10:06, Deepak Gupta wrote: commit 16ad9788 [1] restricted icount to qemu-system only. Although assert in `cpu_loop_exec_tb` is on `icount_enabled()` which is 0 when its qemu-user and debug build starts asserting. Move assert for qemu-system. [1] - https://lists.gnu.org/archive/html/qem

Re: [PULL v3 00/13] Block layer patches

On 8/7/24 04:23, Kevin Wolf wrote: The following changes since commit c659b7b3b4925f8cef486a3ee64e911519495782: Merge tag 'pull-riscv-to-apply-20240806-2' ofhttps://github.com/alistair23/qemu into staging (2024-08-06 17:35:51 +1000) are available in the Git repository at:

[PATCH v3 15/20] target/riscv: shadow stack mmu index for shadow stack instructions

Shadow stack instructions shadow stack mmu index for load/stores. `MMU_IDX_SS_ACCESS` at bit positon 3 is used as shadow stack index. Shadow stack mmu index depend on privilege and SUM bit. If shadow stack accesses happening in user mode, shadow stack mmu index = 0b1000. If shaodw stack access happ

[PATCH v3 20/20] linux-user: Add RISC-V zicfilp support in VDSO

Add zicfilp support in VDSO. VDSO functions need lpad instruction so that userspace could call this function when landing pad extension is enabled. This solution only works when toolchain always use landing pad label 1. Otherwise, If extension is not enabled, lpad instructions will be lui instruct

[PATCH v3 13/20] target/riscv: compressed encodings for sspush and sspopchk

sspush/sspopchk have compressed encodings carved out of zcmops. compressed sspush is designated as c.mop.1 while compressed sspopchk is designated as c.mop.5. Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly c.sspopchk x5 exists while c.sspopchk x1 doesn't. Signed-off-by: Deepak

[PATCH v3 09/20] target/riscv: Add zicfiss extension

zicfiss [1] riscv cpu extension enables backward control flow integrity. This patch sets up space for zicfiss extension in cpuconfig. And imple- ments dependency on zicsr, zimop and zcmop extensions. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepak Gupta Co-developed-by: Jim Shu

[PATCH v3 07/20] target/riscv: zicfilp `lpad` impl and branch tracking

Implements setting lp expected when `jalr` is encountered and implements `lpad` instruction of zicfilp. `lpad` instruction is taken out of auipc x0, . This is an existing HINTNOP space. If `lpad` is target of an indirect branch, cpu checks for 20 bit value in x7 upper with 20 bit value embedded in

[PATCH v3 14/20] target/riscv: mmu changes for zicfiss shadow stack protection

zicfiss protects shadow stack using new page table encodings PTE.W=0, PTE.R=0 and PTE.X=0. This encoding is reserved if zicfiss is not implemented or if shadow stack are not enabled. Loads on shadow stack memory are allowed while stores to shadow stack memory leads to access faults. Shadow stack ac

[PATCH v3 04/20] target/riscv: save and restore elp state on priv transitions

elp state is recorded in *status on trap entry (less privilege to higher privilege) and restored in elp from *status on trap exit (higher to less privilege). Additionally this patch introduces a forward cfi helper function to determine if current privilege has forward cfi is enabled or not based o

[PATCH v3 11/20] target/riscv: tb flag for shadow stack instructions

Shadow stack instructions can be decoded as zimop / zcmop or shadow stack instructions depending on whether shadow stack are enabled at current privilege. This requires a TB flag so that correct TB generation and correct TB lookup happens. `DisasContext` gets a field indicating whether bcfi is enab

[PATCH v3 18/20] target/riscv: add trace-hooks for each case of sw-check exception

Violations to control flow rules setup by zicfilp and zicfiss lead to software check exceptions. To debug and fix such sw check issues in guest , add trace-hooks for each case. Signed-off-by: Jim Shu Signed-off-by: Deepak Gupta --- target/riscv/insn_trans/trans_rvi.c.inc | 6 -- target/ris

[PATCH v3 08/20] disas/riscv: enabled `lpad` disassembly

Signed-off-by: Deepak Gupta Co-developed-by: Jim Shu Co-developed-by: Andy Chiu --- disas/riscv.c | 18 +- disas/riscv.h | 2 ++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index c8364c2b07..c7c92acef7 100644 --- a/disas/riscv.c

[PATCH v3 12/20] target/riscv: implement zicfiss instructions

zicfiss has following instructions - sspopchk: pops a value from shadow stack and compares with x1/x5. If they dont match, reports a sw check exception with tval = 3. - sspush: pushes value in x1/x5 on shadow stack - ssrdp: reads current shadow stack - ssamoswap: swaps contents of shadow sta

[PATCH v3 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp

zicfilp introduces a new state elp ("expected landing pad") in cpu. During normal execution, elp is idle (NO_LP_EXPECTED) i.e not expecting landing pad. On an indirect call, elp moves LP_EXPECTED. When elp is LP_EXPECTED, only a subsquent landing pad instruction can set state back to NO_LP_EXPECTED

[PATCH v3 19/20] linux-user: permit RISC-V CFI dynamic entry in VDSO

RISC-V CFI use new processor-specific dynamic entry in ELF. Permit it in VDSO post-processing script. Signed-off-by: Jim Shu Signed-off-by: Deepak Gupta --- linux-user/gen-vdso-elfn.c.inc | 7 +++ 1 file changed, 7 insertions(+) diff --git a/linux-user/gen-vdso-elfn.c.inc b/linux-user/gen-

[PATCH v3 02/20] target/riscv: Add zicfilp extension

zicfilp [1] riscv cpu extension enables forward control flow integrity. If enabled, all indirect calls must land on a landing pad instruction. This patch sets up space for zicfilp extension in cpuconfig. zicfilp is dependend on zicsr. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepa

[PATCH v3 16/20] disas/riscv: enable disassembly for zicfiss instructions

Enable disassembly for sspush, sspopchk, ssrdp & ssamoswap. Disasembly is only enabled if zimop and zicfiss ext is set to true. Signed-off-by: Deepak Gupta --- disas/riscv.c | 34 ++ disas/riscv.h | 1 + 2 files changed, 35 insertions(+) diff --git a/disas/riscv

[PATCH v3 17/20] disas/riscv: enable disassembly for compressed sspush/sspopchk

sspush and sspopchk have equivalent compressed encoding taken from zcmop. cmop.1 is sspush x1 while cmop.5 is sspopchk x5. Due to unusual encoding for both rs1 and rs2 from space bitfield, this required a new codec. Signed-off-by: Deepak Gupta --- disas/riscv.c | 19 ++- disas/ri

[PATCH v3 05/20] target/riscv: additional code information for sw check

sw check exception support was recently added. This patch further augments sw check exception by providing support for additional code which is provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever sw check exception is raised *tval gets the value deposited in `sw_check_code`. Si

[PATCH v3 10/20] target/riscv: introduce ssp and enabling controls for zicfiss

zicfiss introduces a new state ssp ("shadow stack register") in cpu. ssp is expressed as a new unprivileged csr (CSR_SSP=0x11) and holds virtual address for shadow stack as programmed by software. Shadow stack (for each mode) is enabled via bit3 in *envcfg CSRs. Shadow stack can be enabled for a m

[PATCH v3 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp

zicfilp protects forward control flow (if enabled) by enforcing all indirect call and jmp must land on a landing pad instruction `lpad`. If target of an indirect call or jmp is not `lpad` then cpu/hart must raise a sw check exception with tval = 2. This patch implements the mechanism using TCG. Ta

[PATCH v3 00/20] riscv support for control flow integrity extensions

Sending out v3 for riscv zicfilp and zicfiss extensions support in qemu. I sent out v1 [1] and v2 [2] a while ago. [1] - https://lists.nongnu.org/archive/html/qemu-devel/2024-07/msg06017.html [2] - https://lore.kernel.org/all/ed23bcbc-fdc4-4492-803c-daa958803...@linaro.org/T/ --- v3: - Remove

[PATCH v3 01/20] accel/tcg: restrict assert on icount_enabled to qemu-system

commit 16ad9788 [1] restricted icount to qemu-system only. Although assert in `cpu_loop_exec_tb` is on `icount_enabled()` which is 0 when its qemu-user and debug build starts asserting. Move assert for qemu-system. [1] - https://lists.gnu.org/archive/html/qemu-riscv/2024-01/msg00608.html Signed-o

Re: [PATCH 0/7] various ppc fixes

On 8/6/24 23:13, Nicholas Piggin wrote: Nicholas Piggin (7): ppc/pnv: Fix LPC serirq routing calculation ppc/pnv: Fix LPC POWER8 register sanity check target/ppc: Fix mtDPDES targeting SMT siblings target/ppc: PMIs are level triggered target/ppc: Fix doorbell delivery to threads in

Re: [PATCH] Add plugin bbvgen: basic block icounts for topblocks + simpoints

> Are there any tools that consume this data? Yes. I will post one soon as a follow-up patch. It takes the bbvi.json.gz as input and produces a report sorted by icount of disassembled top blocks. G

Re: [PULL 00/28] Misc HW & UI patches for 2024-08-06

: Merge tag 'for-upstream' ofhttps://gitlab.com/bonzini/qemu into staging (2024-08-06 08:02:34 +1000) are available in the Git repository at: https://github.com/philmd/qemu.git tags/hw-misc-20240806 for you to fetch changes up to e006f0186bff4c66d3dd7a34e08fdae81d606480: docs/spe

Re: [PATCH V2 00/11] Live update: cpr-exec

On 8/5/2024 6:01 AM, Daniel P. Berrangé wrote: On Thu, Jul 18, 2024 at 11:56:33AM -0400, Peter Xu wrote: Steve, On Sun, Jun 30, 2024 at 12:40:23PM -0700, Steve Sistare wrote: What? Thanks for trying out with the cpr-transfer series. I saw that that series missed most of the cc list here, so

Re: [PATCH V2 04/11] migration: stop vm earlier for cpr

On 7/22/2024 9:42 AM, Fabiano Rosas wrote: Steven Sistare writes: On 7/17/2024 2:59 PM, Fabiano Rosas wrote: Steve Sistare writes: Stop the vm earlier for cpr, to guarantee consistent device state when CPR state is saved. Signed-off-by: Steve Sistare --- migration/migration.c | 22 +++

Re: [PATCH v2 4/4] virtio-net: Add support for USO features

On Mon, Aug 05, 2024 at 04:27:43PM +0900, Akihiko Odaki wrote: > On 2024/08/04 22:08, Peter Xu wrote: > > On Sun, Aug 04, 2024 at 03:49:45PM +0900, Akihiko Odaki wrote: > > > On 2024/08/03 1:26, Peter Xu wrote: > > > > On Sat, Aug 03, 2024 at 12:54:51AM +0900, Akihiko Odaki wrote: > > > > > > > > I

Re: [RFC PATCH 04/23] hw/arm: add SVD file for NXP i.MX RT595

On Tue, Aug 6, 2024 at 7:06 AM Alex Bennée wrote: > > Octavian Purdila writes: > > > Picked from: > > > > https://github.com/nxp-mcuxpresso/mcux-soc-svd/blob/main/MIMXRT595S/MIMXRT595S_cm33.xml > > > > NOTE: the file is truncated to keep the email size reasonable. Please > > use the link above an

Re: [PATCH v2 8/9] tests/avocado/machine_aarch64_sbsaref.py: allow for rw usage of image

On 6/8/24 19:31, Cleber Rosa wrote: When the OpenBSD based tests are run in parallel, the previously single instance of the image would become corrupt. Let's give each test its own snapshot. Suggested-by: Alex Bennée ? Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Cleber Rosa ---

Re: [PATCH v2 2/9] tests/avocado: apply proper skipUnless decorator

On 6/8/24 19:31, Cleber Rosa wrote: Commit 9b45cc993 added many cases of skipUnless for the sake of organizing flaky tests. But, Python decorators *must* follow what they decorate, so the newlines added should *not* exist there. Signed-off-by: Cleber Rosa --- tests/avocado/boot_linux_console

Re: [PATCH 2/3] system/vl.c: Expand OpenGL related errors

On 6/8/24 17:20, Antonio Caggiano wrote: Hi On 06/08/2024 15:41, Alex Bennée wrote: Peter Maydell writes: Expand the OpenGL related error messages we produce for various "OpenGL not present/not supported" cases, to hopefully guide the user towards how to fix things. Now if the user tries to

Re: [PATCH 2/2] tests/migration: Introduce multifd compression into guestperf

yong.hu...@smartx.com writes: > From: Hyman Huang > > Guestperf tool does not cover the multifd compression option > currently, it is worth supporting so that developers can > analysis the migration performance with different > compression algorithms. > > Multifd support 4 compression algorithms

RE: [PATCH v3 00/12] hw/misc/aspeed_hace: Fix SG Accumulative Hash Calculations

> To allow 'make check' to succeed at every individual patch, you'll need to > re-order these, and split a couple of patches, to be more or less like this: > > crypto: accumulative hashing API (only define new driver APIs & new public > APIs here) > crypto/hash-glib: Implement new hash API >

Re: [PATCH 7/7] target/ppc: Fix VRMA to not check virtual page class key protection

On Tue, 6 Aug 2024, Nicholas Piggin wrote: Hash virtual real mode addressing is defined by the architecture to not perform virtual page class key protection checks. Signed-off-by: Nicholas Piggin --- target/ppc/mmu-hash64.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --gi

[PULL v3 00/13] Block layer patches

The following changes since commit c659b7b3b4925f8cef486a3ee64e911519495782: Merge tag 'pull-riscv-to-apply-20240806-2' of https://github.com/alistair23/qemu into staging (2024-08-06 17:35:51 +1000) are available in the Git repository at: https://repo.or.cz/qemu/kevin.git tags/fo

Re: [PATCH v2 7/9] tests/avocado/tuxrun_baselines.py: use Avocado's zstd support

On 6.08.2024 19:31, Cleber Rosa wrote: This makes use of the avocado.utils.archive support for zstd. In order to not duplicate code, the skip condition uses a private utility from the module which is going to become public in Avocado versions 103.1 LTS (and also in versions >= 107.0). Reference

Re: [PATCH v2 0/9] Bump Avocado to 103.0 LTS and update tests for compatibility and new features

On 6.08.2024 19:31, Cleber Rosa wrote: This is along overdue update of the Avocado version used in QEMU. It comes a time where the role of the runner and the libraries are being discussed and questioned. These exact commits have been staging on my side for over 30 days now, and I was exceeding

Re: [PATCH 1/2] tests/migration: Nitpick the inconsistent parameters

yong.hu...@smartx.com writes: > From: Hyman Huang > > Signed-off-by: Hyman Huang > --- > tests/migration/guestperf/comparison.py | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tests/migration/guestperf/comparison.py > b/tests/migration/guestperf/comparison.py > index

Complications due to having multiple QAPI schemas (was: [PATCH 5/6] qapi: apply schema prefix to QAPI feature enum constants)

Markus Armbruster writes: > It's not just tests. QAPI-related headers have deteriorated, and pull > in too much. I'll try to clean this up. Thanks! While some cleanup is certainly possible and probably useful, I don't think I can completely solve the problem that way. Not counting tests, we

[PATCH v2 4/9] tests/avocado: machine aarch64: standardize location and RO access

The tests under machine_aarch64_virt.py and machine_aarch64_sbsaref.py should not be writing to the ISO files. By adding "media=cdrom" the "ro" is autmatically set. While at it, let's use a single code style and hash for the ISO url. Signed-off-by: Cleber Rosa --- tests/avocado/machine_aarch64

[PATCH v2 3/9] tests/avocado: add cdrom permission related tests

The "media=cdrom" parameter is also used on some Avocado tests as a way to protect files from being written. The tests here bring a more fundamental check that this behavior can be trusted. Signed-off-by: Cleber Rosa --- tests/avocado/cdrom.py | 41 + 1 f

[PATCH v2 2/9] tests/avocado: apply proper skipUnless decorator

Commit 9b45cc993 added many cases of skipUnless for the sake of organizing flaky tests. But, Python decorators *must* follow what they decorate, so the newlines added should *not* exist there. Signed-off-by: Cleber Rosa --- tests/avocado/boot_linux_console.py | 1 - tests/avocado/intel_iommu.py

[PATCH v2 7/9] tests/avocado/tuxrun_baselines.py: use Avocado's zstd support

This makes use of the avocado.utils.archive support for zstd. In order to not duplicate code, the skip condition uses a private utility from the module which is going to become public in Avocado versions 103.1 LTS (and also in versions >= 107.0). Reference: https://github.com/avocado-framework/av

[PATCH v2 6/9] tests/avocado/boot_xen.py: fetch kernel during test setUp()

The kernel is a common blob used in all tests. By moving it to the setUp() method, the "fetch asset" plugin will recognize the kernel and attempt to fetch it and cache it before the tests are started. Signed-off-by: Cleber Rosa --- tests/avocado/boot_xen.py | 13 ++--- 1 file changed, 6

[PATCH v2 9/9] Avocado tests: allow for parallel execution of tests

The updated Avocado version allows for the execution of tests in parallel. While on a CI environment it may not be a good idea to increase the parallelization level in a single runner, developers may leverage that on specific CI runners or on their development environments. This also multiplies t

[PATCH v2 5/9] tests/avocado: simplify parameters on fetch_asset with name only

When an asset has a single location, it's possible to use that URI as the name of the asset. Reference: https://avocado-framework.readthedocs.io/en/103.0/api/utils/avocado.utils.html#avocado.utils.asset.Asset Reference: https://avocado-framework.readthedocs.io/en/103.0/api/test/avocado.html#avoc

[PATCH v2 8/9] tests/avocado/machine_aarch64_sbsaref.py: allow for rw usage of image

When the OpenBSD based tests are run in parallel, the previously single instance of the image would become corrupt. Let's give each test its own snapshot. Signed-off-by: Cleber Rosa --- tests/avocado/machine_aarch64_sbsaref.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/

[PATCH v2 1/9] Bump avocado to 103.0

This bumps Avocado to latest the LTS release. An LTS release is one that can receive bugfixes and guarantees stability for a much longer period and has incremental minor releases made. Even though the 103.0 LTS release is pretty a rewrite of Avocado when compared to 88.1, the behavior of all exis

[PATCH v2 0/9] Bump Avocado to 103.0 LTS and update tests for compatibility and new features

This is a *long* overdue update of the Avocado version used in QEMU. It comes a time where the role of the runner and the libraries are being discussed and questioned. These exact commits have been staging on my side for over 30 days now, and I was exceeding what I should in terms of testing befor

Re: [PATCH v16 02/13] virtio-gpu: Move fence_poll timer to VirtIOGPUGL

Dmitry Osipenko writes: > Move fence_poll timer to VirtIOGPUGL for consistency with cmdq_resume_bh > that are used only by GL device. > > Signed-off-by: Dmitry Osipenko Reviewed-by: Alex Bennée -- Alex Bennée Virtualisation Tech Lead @ Linaro

[PATCH] net: Fix '-net nic,model=' for non-help arguments

From: David Woodhouse Oops, don't *delete* the model option when checking for 'help'. Fixes: 64f75f57f9d2 ("net: Reinstate '-net nic, model=help' output as documented in man page") Reported-by: Hans Signed-off-by: David Woodhouse Cc: qemu-sta...@nongnu.org --- This whole mess of alternative c

Re: [PATCH] hw/display: Add SSD1306 dot matrix display controller support

Hi Peter, I responded to this over 3mo ago and haven't seen a reply. I'm assuming it got lost so I'll try again. For some background, I put together an internal Yocto training targeting a Raspberry Pi Zero board with a small SSD1306 based OLED display (ex. https://www.adafruit.com/product/3527).

Re: [PATCH] migration: Refine the convergence detection

On Mon, Aug 05, 2024 at 03:03:27PM +0800, Yong Huang wrote: > Sorry for the late reply. > > On Wed, Jul 31, 2024 at 4:01 AM Peter Xu wrote: > > > On Wed, Jul 24, 2024 at 07:39:29PM +0800, Hyman Huang wrote: > > > Currently, the convergence algorithm determines that the migration > > > cannot con

Re: [PATCH 4/4] virtio-mem: Add support for suspend+wake-up with plugged memory

On 06.08.24 18:07, Juraj Marcin wrote: Before, the virtio-mem device would unplug all the memory with any reset of the device, including during the wake-up of the guest from a suspended state. Due to this, the virtio-mem driver in the Linux kernel disallowed suspend-to-ram requests in the guest w

Re: [PATCH 3/4] virtio-mem: Implement Resettable interface instead of using LegacyReset

On 06.08.24 18:07, Juraj Marcin wrote: LegacyReset does not pass ResetType to the reset callback method, which the new Resettable interface uses. Due to this, virtio-mem cannot use the new RESET_TYPE_WAKEUP to skip reset during wake-up from a suspended state. This patch adds the Resettable inter

Re: [PATCH 2/4] reset: Add RESET_TYPE_WAKEUP

On 06.08.24 18:07, Juraj Marcin wrote: Some devices need to distinguish cold start reset from waking up from a suspended state. This patch adds new value to the enum, and updates the i386 wakeup method to use this new reset type. Signed-off-by: Juraj Marcin --- docs/devel/reset.rst| 7 +++

Re: [PATCH 1/4] reset: Use ResetType for qemu_devices_reset() and MachineClass->reset()

On 06.08.24 18:07, Juraj Marcin wrote: Currently, both qemu_devices_reset() and MachineClass->reset() use ShutdownCause for the reason of the reset. However, the Resettable interface uses ResetState, so ShutdownCause needs to be translated to ResetType somewhere. Translating it qemu_devices_reset

Re: [PATCH] target/hexagon: don't look for static glib

On 8/5/2024 5:49 AM, Alyssa Ross wrote: When cross compiling QEMU configured with --static, I've been getting configure errors like the following: Build-time dependency glib-2.0 found: NO ../target/hexagon/meson.build:303:15: ERROR: Dependency lookup for glib-2.0 with method 'pkgco

[PATCH 3/4] virtio-mem: Implement Resettable interface instead of using LegacyReset

LegacyReset does not pass ResetType to the reset callback method, which the new Resettable interface uses. Due to this, virtio-mem cannot use the new RESET_TYPE_WAKEUP to skip reset during wake-up from a suspended state. This patch adds the Resettable interface to the VirtioMemClass interface list

[PATCH 4/4] virtio-mem: Add support for suspend+wake-up with plugged memory

Before, the virtio-mem device would unplug all the memory with any reset of the device, including during the wake-up of the guest from a suspended state. Due to this, the virtio-mem driver in the Linux kernel disallowed suspend-to-ram requests in the guest when the VIRTIO_MEM_F_PERSISTENT_SUSPEND f

[PATCH 1/4] reset: Use ResetType for qemu_devices_reset() and MachineClass->reset()

Currently, both qemu_devices_reset() and MachineClass->reset() use ShutdownCause for the reason of the reset. However, the Resettable interface uses ResetState, so ShutdownCause needs to be translated to ResetType somewhere. Translating it qemu_devices_reset() makes adding new reset types harder, a

[PATCH 0/4] virtio-mem: Implement support for suspend+wake-up with plugged memory

Currently, the virtio-mem device would unplug all the memory with any reset request, including when the machine wakes up from a suspended state (deep sleep). This would lead to a loss of the contents of the guest memory and therefore is disabled by the virtio-mem Linux Kernel driver unless the VIRT

[PATCH 2/4] reset: Add RESET_TYPE_WAKEUP

Some devices need to distinguish cold start reset from waking up from a suspended state. This patch adds new value to the enum, and updates the i386 wakeup method to use this new reset type. Signed-off-by: Juraj Marcin --- docs/devel/reset.rst| 7 +++ hw/i386/pc.c| 2 +- incl

Re: [PATCH v2 13/13] target/riscv: Enable PMU related extensions to preferred rule

On 8/6/24 5:46 AM, Andrew Jones wrote: On Tue, Jul 23, 2024 at 04:30:10PM GMT, Atish Patra wrote: Counter delegation/configuration extension requires the following extensions to be enabled. 1. Smcdeleg - To enable counter delegation from M to S 2. S[m|s]csrind - To enable indirect access CSR

Re: [PATCH v3 00/12] hw/misc/aspeed_hace: Fix SG Accumulative Hash Calculations

On Mon, Aug 05, 2024 at 03:50:35PM +, Alejandro Zeise wrote: > The goal of this patch series is to fix accumulative hashing support in the > Aspeed HACE module. The issue that stemmed this patch was a failure to boot an > OpenBMC image using the "ast2600-evb" machine. The U-boot > 2019.04 load

Re: [PATCH v3 01/12] crypto: accumulative hashing API

On Mon, Aug 05, 2024 at 03:50:36PM +, Alejandro Zeise wrote: > Changes the hash API to support accumulative hashing. > Hash objects are created with "qcrypto_hash_new", > updated with data with "qcrypto_hash_update", and > the hash obtained with "qcrypto_hash_finalize". > > These changes bring

[PATCH 2/2] tests/migration: Introduce multifd compression into guestperf

From: Hyman Huang Guestperf tool does not cover the multifd compression option currently, it is worth supporting so that developers can analysis the migration performance with different compression algorithms. Multifd support 4 compression algorithms currently: zlib, zstd, qpl, uadk To request

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