Sending out v3 for riscv zicfilp and zicfiss extensions support in qemu. I sent out v1 [1] and v2 [2] a while ago.
[1] - https://lists.nongnu.org/archive/html/qemu-devel/2024-07/msg06017.html [2] - https://lore.kernel.org/all/ed23bcbc-fdc4-4492-803c-daa958803...@linaro.org/T/ --- v3: - Removed prctl specific patches because they need to be upstream in kernel first. - As suggested by Richard, added TB flag if fcfi enabled - Re-worked translation for landing pad and shadow stack instructions to not require helper. - tcg helpers only for cfi violation cases so that trace hooks can be placed. - Style changes. - fixes assert condition in accel/tcg v2: - added missed file (in v1) for shadow stack instructions implementation. Deepak Gupta (20): accel/tcg: restrict assert on icount_enabled to qemu-system target/riscv: Add zicfilp extension target/riscv: Introduce elp state and enabling controls for zicfilp target/riscv: save and restore elp state on priv transitions target/riscv: additional code information for sw check target/riscv: tracking indirect branches (fcfi) for zicfilp target/riscv: zicfilp `lpad` impl and branch tracking disas/riscv: enabled `lpad` disassembly target/riscv: Add zicfiss extension target/riscv: introduce ssp and enabling controls for zicfiss target/riscv: tb flag for shadow stack instructions target/riscv: implement zicfiss instructions target/riscv: compressed encodings for sspush and sspopchk target/riscv: mmu changes for zicfiss shadow stack protection target/riscv: shadow stack mmu index for shadow stack instructions disas/riscv: enable disassembly for zicfiss instructions disas/riscv: enable disassembly for compressed sspush/sspopchk target/riscv: add trace-hooks for each case of sw-check exception linux-user: permit RISC-V CFI dynamic entry in VDSO linux-user: Add RISC-V zicfilp support in VDSO accel/tcg/cpu-exec.c | 2 +- disas/riscv.c | 71 +++++++- disas/riscv.h | 4 + linux-user/gen-vdso-elfn.c.inc | 7 + linux-user/riscv/vdso-64.so | Bin 3944 -> 4128 bytes linux-user/riscv/vdso.S | 50 ++++++ target/riscv/cpu.c | 17 ++ target/riscv/cpu.h | 28 +++ target/riscv/cpu_bits.h | 29 +++ target/riscv/cpu_cfg.h | 2 + target/riscv/cpu_helper.c | 167 +++++++++++++++++- target/riscv/cpu_user.h | 1 + target/riscv/csr.c | 106 +++++++++++ target/riscv/helper.h | 3 + target/riscv/insn16.decode | 4 + target/riscv/insn32.decode | 23 ++- target/riscv/insn_trans/trans_rva.c.inc | 55 ++++++ target/riscv/insn_trans/trans_rvi.c.inc | 68 +++++++ target/riscv/insn_trans/trans_rvzicfiss.c.inc | 155 ++++++++++++++++ target/riscv/internals.h | 4 + target/riscv/op_helper.c | 49 +++++ target/riscv/pmp.c | 5 + target/riscv/pmp.h | 3 +- target/riscv/tcg/tcg-cpu.c | 20 +++ target/riscv/trace-events | 6 + target/riscv/translate.c | 75 ++++++++ 26 files changed, 945 insertions(+), 9 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvzicfiss.c.inc -- 2.44.0
