Avihai Horon writes:
> On 31/07/2024 8:12, Markus Armbruster wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> Avihai Horon writes:
>>
>>> On 30/07/2024 15:22, Markus Armbruster wrote:
Avihai, there's a question for you on VfioMigrationState.
Daniel P. Be
I apologize for the delay.
Daniel Henrique Barboza writes:
> We're not honouring KVM options that are provided by any -accel option
> aside from the first. In this example:
>
> qemu-system-riscv64 -accel kvm,riscv-aia=emul (...) \
> -accel kvm,riscv-aia=hwaccel
>
> 'riscv-aia' will be set to
On 7/31/24 08:19, Philippe Mathieu-Daudé wrote:
The following changes since commit ef009e4b4dc0421464008e6e303b892141ede579:
Merge tag 's390x-20240730' ofhttps://github.com/davidhildenbrand/qemu into
staging (2024-07-30 19:21:58 +1000)
are available in the Git repository at:
On 7/31/24 02:22, Alex Bennée wrote:
The following changes since commit 8617cb073ca9fa5588d7afad5c81b7aa6cd02f26:
Merge tag 'pull-misc-20240730' ofhttps://gitlab.com/rth7680/qemu into
staging (2024-07-30 11:12:42 +1000)
are available in the Git repository at:
https://gitlab.c
Em Tue, 30 Jul 2024 07:36:32 -0400
"Michael S. Tsirkin" escreveu:
> On Tue, Jul 30, 2024 at 01:24:30PM +0200, Igor Mammedov wrote:
> > On Mon, 22 Jul 2024 08:45:58 +0200
> > Mauro Carvalho Chehab wrote:
> >
> > > There is one reference to ACPI 4.0 and several references
> > > to ACPI 6.x vers
On 31/07/2024 8:12, Markus Armbruster wrote:
External email: Use caution opening links or attachments
Avihai Horon writes:
On 30/07/2024 15:22, Markus Armbruster wrote:
Avihai, there's a question for you on VfioMigrationState.
Daniel P. Berrangé writes:
On Tue, Jul 30, 2024 at 10:10:1
Overview
Split "Power11 support for QEMU" into 2 patch series: pseries & powernv.
This patch series is for pseries support for Power11.
As Power11 core is same as Power10, hence much of the code has been reused from
Power10.
Power11 was added in Linux in:
commit c2ed087ed35c ("po
From: Harsh Prateek Bora
Power9/10 initialization code consists of a lot of logical OR of
various flag bits as supported by respective Power platform during its
initialization, most of which is duplicated and only selected bits are
added or removed as needed with each new platform support being a
Add sPAPR CPU Core definition for Power11
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: David Gibson
Cc: Frédéric Barrat
Cc: Harsh Prateek Bora
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
Signed-o
Introduce 'PnvChipClass::spapr_logical_pvr' to know corresponding logical
PVR of a PowerPC CPU.
This helps to have a one-to-one mapping between PVR and logical PVR for
a CPU, and used in a later commit to handle cases where PCR of two
generations of Power chip is same, which causes regressions with
Add CPU target code to add support for new Power11 Processor.
Power11 core is same as Power10, hence reuse functions defined for
Power10.
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Frédéric Barrat
Cc: Harsh Prateek Bora
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas
Power11 has the same PCR (Processor Compatibility Register) value, as
Power10.
Due to this, QEMU considers Power11 as a valid compat-mode for Power10,
ie. earlier it was possible to run QEMU with '-M
pseries,max-compat-mode=power11 --cpu power10'
Same PCR also introduced a regression where `-M p
Em Tue, 30 Jul 2024 16:11:42 +0800
Zhao Liu escreveu:
> Hi Mauro,
>
> On Mon, Jul 29, 2024 at 03:21:06PM +0200, Mauro Carvalho Chehab wrote:
> > Date: Mon, 29 Jul 2024 15:21:06 +0200
> > From: Mauro Carvalho Chehab
> > Subject: [PATCH v4 2/6] arm/virt: Wire up GPIO error source for ACPI / GHES
Em Tue, 30 Jul 2024 10:36:15 +0200
Igor Mammedov escreveu:
> On Mon, 22 Jul 2024 08:45:54 +0200
> Mauro Carvalho Chehab wrote:
>
> > From: Jonathan Cameron
> >
> > Creates a GED - Generic Event Device and set a GPIO to
> > be used or error injection.
>
> QEMU already has GED device, so que
Avihai Horon writes:
> On 30/07/2024 15:22, Markus Armbruster wrote:
>>
>> Avihai, there's a question for you on VfioMigrationState.
>>
>> Daniel P. Berrangé writes:
>>
>>> On Tue, Jul 30, 2024 at 10:10:15AM +0200, Markus Armbruster wrote:
[...]
>> * VfioMigrationState
>>
>>Can't see why t
On 7/31/24 03:03, Daniel P. Berrangé wrote:
Many tests need to access assets stored on remote sites. We don't want
to download these during test execution when run by meson, since this
risks hitting test timeouts when data transfers are slow.
Add support for pre-emptive caching of assets by sett
ju...@oro.sh writes:
> 31 July 2024 at 02:12, "Dr. David Alan Gilbert" wrote:
>
> Hello Dr. Gilbert,
>
>>
>> * Josh Junon (ju...@oro.sh) wrote:
>>
>> Hi Josh,
>>
>> >
>> > This commit adds a new QMP/HMP command `memtranslate`,
>> > which translates a virtual address to a physical address
>> >
On 7/30/24 19:21, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci.c | 8
hw/sd/trace-events | 1 +
2 files changed, 9 insertions(+)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 8293d83556..66b9364e9e 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd
On 7/30/24 19:21, Philippe Mathieu-Daudé wrote:
We neglected to clear the @data_count index on ADMA error,
allowing to trigger assertion in sdhci_read_dataport() or
sdhci_write_dataport().
Cc:qemu-sta...@nongnu.org
Fixes: d7dfca0807 ("hw/sdhci: introduce standard SD host controller")
Reported-by
On 7/30/24 19:21, Philippe Mathieu-Daudé wrote:
Guest should not try to read the DAT lines from invalid
command state. If it still insists to do so, return a
dummy value.
Cc:qemu-sta...@nongnu.org
Fixes: e2dec2eab0 ("hw/sd/sdcard: Remove default case in read/write on DAT
lines")
Reported-by: Zh
On 7/30/24 19:21, Philippe Mathieu-Daudé wrote:
On error the DAT lines are left unmodified to their
previous states. QEMU returns 0x00 for convenience.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/hw/sd/s
On 7/30/24 22:24, Clément Léger wrote:
Instead of using a slow implementation to close all open fd after
forking, use qemu_close_all_open_fd().
Signed-off-by: Clément Léger
---
net/tap.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson
On Tue, Jul 30, 2024 at 6:23 PM Akihiko Odaki wrote:
>
> On 2024/07/30 12:45, Jason Wang wrote:
> > On Tue, Jul 30, 2024 at 11:29 AM Akihiko Odaki
> > wrote:
> >>
> >> On 2024/07/30 12:17, Jason Wang wrote:
> >>> On Tue, Jul 30, 2024 at 11:12 AM Akihiko Odaki
> >>> wrote:
>
> On 2024
On 7/30/24 22:24, Clément Léger wrote:
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
index a6749d9f9b..e7bffaea16 100644
--- a/util/oslib-posix.c
+++ b/util/oslib-posix.c
@@ -808,11 +808,14 @@ int qemu_msync(void *addr, size_t length, int fd)
return msync(addr, length, MS_SYNC);
}
On Wed, Jul 31, 2024 at 5:33 AM Michael S. Tsirkin wrote:
>
> On Tue, Jul 30, 2024 at 04:03:53PM -0400, Peter Xu wrote:
> > On Tue, Jul 30, 2024 at 03:22:50PM -0400, Michael S. Tsirkin wrote:
> > > This is not what we did historically. Why should we start now?
> >
> > It's a matter of whether we s
On 7/30/24 22:24, Clément Léger wrote:
The same code is used twice to actually close all open file descriptors
after forking. Factorize it in a single place.
Signed-off-by: Clément Léger
---
net/tap.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
Review
On 7/30/24 22:24, Clément Léger wrote:
+/*
+ * Close all open file descriptors.
+ */
+void qemu_close_all_open_fd(void)
+{
+int open_max = sysconf(_SC_OPEN_MAX);
+int i;
+
+if (qemu_close_all_open_fd_close_range()) {
+return;
+}
+
+if (qemu_close_all_open_fd_proc()) {
On 7/30/24 22:24, Clément Léger wrote:
Move close_all_open_fds() in oslib-posix, rename it
qemu_close_all_open_fds() and export it.
Signed-off-by: Clément Léger
---
include/qemu/osdep.h| 7 +++
system/async-teardown.c | 37 +
util/oslib-posix.c
On 7/31/24 02:03, Peter Maydell wrote:
Now that we've implemented the required behaviour for FEAT_EBF16, we
can enable it for the "max" CPU type, list it in our documentation,
and delete a TODO comment about it being missing.
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 1
On 7/31/24 02:03, Peter Maydell wrote:
Implement the FPCR.EBF=1 semantics for bfdotadd() operations:
* is_ebf() sets up fpst and fpst_odd
* bfdotadd_ebf() implements the fused paired-multiply-and-add
operation that we need
The paired-multiply-and-add is similar to f16_dotadd() and
we use
On 7/31/24 02:03, Peter Maydell wrote:
@@ -2790,7 +2790,7 @@ DO_MMLA_B(gvec_usmmla_b, do_usmmla_b)
* BFloat16 Dot Product
*/
-float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2)
+bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)
{
/* FPCR is igno
On 7/31/24 02:03, Peter Maydell wrote:
We use bfdotadd() in four callsites for various helper functions. Currently
this all assumes that we have the FPCR.EBF=0 semantics. For FPCR.EBF=1
we will need to:
* call a different routine to bfdotadd() because we need to do a
fused multiply-add rath
On 7/31/24 02:03, Peter Maydell wrote:
Pass the env pointer through to the gvec_bfmmla helper,
so we can use it to add support for FEAT_EBF16.
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 4 ++--
target/arm/tcg/translate-a64.c | 2 +-
target/arm/tcg/translate-neon.c |
On 7/31/24 02:03, Peter Maydell wrote:
Pass the env pointer through to the gvec_bfdot_idx helper,
so we can use it to add support for FEAT_EBF16.
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 4 ++--
target/arm/tcg/translate-a64.c | 11 ++-
target/arm/tcg/tran
On 7/31/24 02:03, Peter Maydell wrote:
Pass the env pointer through to the gvec_bfdot helper,
so we can use it to add support for FEAT_EBF16.
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 4 ++--
target/arm/tcg/translate-a64.c | 27 -
target/ar
On 7/31/24 02:03, Peter Maydell wrote:
To implement the FEAT_EBF16 semantics, we are going to need
the CPUARMState env pointer in every helper function which calls
bfdotadd().
Pass the env pointer through from generated code to the sme_bfmopa
helper. (We'll add the code that uses it when we've a
On 7/31/24 02:02, Peter Maydell wrote:
FEAT_EBF16 adds one new bit to the FPCR floating point control
register. Allow this bit to be read and written when the ID
registers indicate the presence of the feature.
Note that because this new bit is not in FPSCR_FPCR_MASK the bit is
not visible in th
20240726-1' ofhttps://gitlab.com/npiggin/qemu
into staging (2024-07-26 15:10:45 +1000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20240730
for you to fetch changes up to 73188068d7ba40c8a37b4763db38bb1ce24ca07d:
Define a hexagon_cpu_properties list to match the idiom used
by other targets.
Signed-off-by: Brian Cain
---
target/hexagon/cpu.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 64cc05cca7..93579fbb15 10064
For now, v66 behavior is the same as other CPUs.
Signed-off-by: Brian Cain
---
target/hexagon/cpu-qom.h | 1 +
target/hexagon/cpu.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h
index da92fe7468..0b149bd5fe 100644
--- a/target/hexa
31 July 2024 at 02:12, "Dr. David Alan Gilbert" wrote:
Hello Dr. Gilbert,
>
> * Josh Junon (ju...@oro.sh) wrote:
>
> Hi Josh,
>
> >
> > This commit adds a new QMP/HMP command `memtranslate`,
> >
> > which translates a virtual address to a physical address
> >
> > using the guest's MMU.
>
On 30 July 2024 21:45:53 BST, "Michael S. Tsirkin" wrote:
>On Tue, Jul 30, 2024 at 08:04:17PM +0100, David Woodhouse wrote:
>> On 30 July 2024 18:53:18 BST, "Michael S. Tsirkin" wrote:
>> >We don't want to manually sync headers with Linux.
>>
>> Indeed. I was briefly tempted to fake it, but figu
* Josh Junon (ju...@oro.sh) wrote:
Hi Josh,
> This commit adds a new QMP/HMP command `memtranslate`,
> which translates a virtual address to a physical address
> using the guest's MMU.
>
> This uses the same mechanism that `[p]memsave` does to
> perform the translation.
>
> This commit also fix
Hi Alex,
> On Jul 30, 2024, at 22:25, Alex Bennée wrote:
>
> Itaru Kitayama writes:
>
>> Hi,
>>
>> Executing virt-install with the following options:
>>
>> sudo virt-install --machine=virt --arch=aarch64 --name=test8 --disk
>> path=/var/lib/libvirt/images/jammy.qcow2,format=qcow2,device=disk
On 7/31/24 07:54, Ilya Leoshkevich wrote:
While qemu-system can set tb-size using -accel tcg,tb-size=n, there
is no similar knob for qemu-user. Add one in a way similar to how
one-insn-per-tb is already handled.
Signed-off-by: Ilya Leoshkevich
---
linux-user/main.c | 12
1 file c
On 7/31/24 01:58, Peter Maydell wrote:
-void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn,
- void *vpm, void *vst, uint32_t desc)
+void HELPER(sme_fmopa_h)(CPUARMState *env,
+ void *vza, void *vzn, void *vzm, void *vpn,
+
From: Cleber Rosa
The asset used in the mentioned test gets truncated before it's used
in the test. This means that the file gets modified, and thus the
asset's expected hash doesn't match anymore. This causes cache misses
and re-downloads every time the test is re-run.
Let's make a copy of th
From: Cleber Rosa
Avocado's fetchasset plugin runs before the actual Avocado job (and
any test). It analyses the test's code looking for occurrences of
"self.fetch_asset()" in the either the actual test or setUp() method.
It's not able to fully analyze all code, though.
The way these tests are
From: Thomas Weißschuh
To make sure that the QAPI description stays valid, add a testcase.
Suggested-by: Philippe Mathieu-Daudé
Link:
https://lore.kernel.org/qemu-devel/d9ce0234-4beb-4b90-b14c-76810d3b8...@linaro.org/
Reviewed-by: Daniel P. Berrangé
Acked-by: Markus Armbruster
Signed-off-by:
From: Peter Maydell
Our official support policy only supports the most recent two
versions of macOS (currently macOS 13 Ventura and macOS 14 Sonoma),
and we already have code that assumes at least macOS 12 Monterey or
better. In commit 2d27c91e2b72ac7 we dropped some of the back-compat
code for
From: Peter Maydell
In newer versions of Sphinx the env.doc2path() API is going to change
to return a Path object rather than a str. This was originally visible
in Sphinx 8.0.0rc1, but has been rolled back for the final 8.0.0
release. However it will probably emit a deprecation warning and is
lik
From: Cleber Rosa
The SSL certificate installed at mipsdistros.mips.com has expired:
0 s:CN = mipsdistros.mips.com
i:C = US, O = Amazon, OU = Server CA 1B, CN = Amazon
a:PKEY: rsaEncryption, 2048 (bit); sigalg: RSA-SHA256
v:NotBefore: Dec 23 00:00:00 2019 GMT; NotAfter: Jan 23 12:00:00 2021
The following changes since commit ef009e4b4dc0421464008e6e303b892141ede579:
Merge tag 's390x-20240730' of https://github.com/davidhildenbrand/qemu into
staging (2024-07-30 19:21:58 +1000)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/docs-testin
This commit adds a new QMP/HMP command `memtranslate`,
which translates a virtual address to a physical address
using the guest's MMU.
This uses the same mechanism that `[p]memsave` does to
perform the translation.
This commit also fixes a long standing issue of `[p]memsave`
not properly handling
On Tue, Jul 30, 2024 at 05:32:48PM -0400, Michael S. Tsirkin wrote:
> On Tue, Jul 30, 2024 at 04:03:53PM -0400, Peter Xu wrote:
> > On Tue, Jul 30, 2024 at 03:22:50PM -0400, Michael S. Tsirkin wrote:
> > > This is not what we did historically. Why should we start now?
> >
> > It's a matter of whet
Thanks Peter!
For the macOS 13 comment just so I’m clear, you’re saying the minimum we
support is
13 now so the conditional compilation for those isn’t required anymore as well?
I suppose
that tracks given the wording that we support the last two macOS releases at
any given
time, that kind of
While qemu-system can set tb-size using -accel tcg,tb-size=n, there
is no similar knob for qemu-user. Add one in a way similar to how
one-insn-per-tb is already handled.
Signed-off-by: Ilya Leoshkevich
---
linux-user/main.c | 12
1 file changed, 12 insertions(+)
diff --git a/linux-
On Tue, Jul 30, 2024 at 04:03:53PM -0400, Peter Xu wrote:
> On Tue, Jul 30, 2024 at 03:22:50PM -0400, Michael S. Tsirkin wrote:
> > This is not what we did historically. Why should we start now?
>
> It's a matter of whether we still want migration to randomly fail, like
> what this patch does.
>
On Tue, Jul 30, 2024 at 08:04:17PM +0100, David Woodhouse wrote:
> On 30 July 2024 18:53:18 BST, "Michael S. Tsirkin" wrote:
> >We don't want to manually sync headers with Linux.
>
> Indeed. I was briefly tempted to fake it, but figured it might get lost if we
> subsequently do run the script to
Ping for my patch from last Friday.
https://patchew.org/QEMU/20240719102053.316744-1-...@dprinz.de/
https://lore.kernel.org/qemu-devel/20240719102053.316744-1-...@dprinz.de/
On 19.07.24 12:20, Dominic Prinz wrote:
This patch implements the periodic and the swsmi ICH9 chipset timer. They are
es
On Tue, Jul 30, 2024 at 03:22:50PM -0400, Michael S. Tsirkin wrote:
> This is not what we did historically. Why should we start now?
It's a matter of whether we still want migration to randomly fail, like
what this patch does.
Or any better suggestions? I'm definitely open to that.
Thanks,
--
On Wed, Jul 24, 2024 at 07:39:29PM +0800, Hyman Huang wrote:
> Currently, the convergence algorithm determines that the migration
> cannot converge according to the following principle:
> The dirty pages generated in current iteration exceed a specific
> percentage (throttle-trigger-threshold, 50 b
From: Harsh Prateek Bora
Power9/10 initialization code consists of a lot of logical OR of
various flag bits as supported by respective Power platform during its
initialization, most of which is duplicated and only selected bits are
added or removed as needed with each new platform support being a
Power11 has the same PCR (Processor Compatibility Register) value, as
Power10.
Due to this, QEMU considers Power11 as a valid compat-mode for Power10,
ie. earlier it was possible to run QEMU with '-M
pseries,max-compat-mode=power11 --cpu power10'
Same PCR also introduced a regression where `-M p
Add sPAPR CPU Core definition for Power11
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: David Gibson
Cc: Frédéric Barrat
Cc: Harsh Prateek Bora
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
Signed-o
Add CPU target code to add support for new Power11 Processor.
Power11 core is same as Power10, hence reuse functions defined for
Power10.
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Frédéric Barrat
Cc: Harsh Prateek Bora
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas
Introduce 'PnvChipClass::spapr_logical_pvr' to know corresponding logical
PVR of a PowerPC CPU.
This helps to have a one-to-one mapping between PVR and logical PVR for
a CPU, and used in a later commit to handle cases where PCR of two
generations of Power chip is same, which causes regressions with
Overview
Split "Power11 support for QEMU" into 2 patch series: pseries & powernv.
This patch series is for pseries support for Power11.
As Power11 core is same as Power10, hence much of the code has been reused from
Power10.
Power11 was added in Linux in:
commit c2ed087ed35c ("po
On Tue, Jul 30, 2024 at 03:11:03PM -0400, Peter Xu wrote:
> On Tue, Jul 30, 2024 at 07:46:12PM +0100, Daniel P. Berrangé wrote:
> > On Tue, Jul 30, 2024 at 02:13:51PM -0400, Peter Xu wrote:
> > > On Mon, Jul 29, 2024 at 06:26:41PM +0100, Daniel P. Berrangé wrote:
> > > > On Mon, Jul 29, 2024 at 01:
On Tue, Jul 30, 2024 at 07:46:12PM +0100, Daniel P. Berrangé wrote:
> On Tue, Jul 30, 2024 at 02:13:51PM -0400, Peter Xu wrote:
> > On Mon, Jul 29, 2024 at 06:26:41PM +0100, Daniel P. Berrangé wrote:
> > > On Mon, Jul 29, 2024 at 01:00:30PM -0400, Peter Xu wrote:
> > > > On Mon, Jul 29, 2024 at 04:
On 30 July 2024 18:53:18 BST, "Michael S. Tsirkin" wrote:
>We don't want to manually sync headers with Linux.
Indeed. I was briefly tempted to fake it, but figured it might get lost if we
subsequently do run the script to automatically merge from Linux, before the
guest driver is merged there.
On Fri, Jul 19, 2024 at 12:20:53PM +0200, Dominic Prinz wrote:
> This patch implements the periodic and the swsmi ICH9 chipset timer. They are
> especially useful when prototyping UEFI firmware (e.g. with EDK2's OVMF)
> with QEMU.
>
> This includes that writes to the SMI_STS register are enabled f
On Tue, Jul 30, 2024 at 02:13:51PM -0400, Peter Xu wrote:
> On Mon, Jul 29, 2024 at 06:26:41PM +0100, Daniel P. Berrangé wrote:
> > On Mon, Jul 29, 2024 at 01:00:30PM -0400, Peter Xu wrote:
> > > On Mon, Jul 29, 2024 at 04:58:03PM +0100, Daniel P. Berrangé wrote:
> > > >
> > > > We've got two mutu
On 30/7/24 19:03, Daniel P. Berrangé wrote:
This series is an update to Thomas' v2:
https://lists.nongnu.org/archive/html/qemu-devel/2024-07/msg05805.html
wherein Thomas suggested someone could do the asset caching updates
while he is on vacation:
https://lists.nongnu.org/archive/html/qe
On 30/7/24 11:59, Peter Maydell wrote:
Our official support policy only supports the most recent two
versions of macOS (currently macOS 13 Ventura and macOS 14 Sonoma),
and we already have code that assumes at least macOS 12 Monterey or
better. In commit 2d27c91e2b72ac7 we dropped some of the ba
On 30/7/24 12:14, Peter Maydell wrote:
On Tue, 30 Jul 2024 at 11:05, Philippe Mathieu-Daudé wrote:
On 29/7/24 17:36, Daniel P. Berrangé wrote:
On Mon, Jul 29, 2024 at 05:27:00PM +0200, Philippe Mathieu-Daudé wrote:
Thomas Huth (9):
python: Install pycotap in our venv if necessary
t
On Mon, Jul 29, 2024 at 06:26:41PM +0100, Daniel P. Berrangé wrote:
> On Mon, Jul 29, 2024 at 01:00:30PM -0400, Peter Xu wrote:
> > On Mon, Jul 29, 2024 at 04:58:03PM +0100, Daniel P. Berrangé wrote:
> > >
> > > We've got two mutually conflicting goals with the machine type
> > > definitions.
> >
On Tue, Jul 30, 2024 at 02:23:46AM +0900, Akihiko Odaki wrote:
> On 2024/07/30 2:00, Peter Xu wrote:
> > On Mon, Jul 29, 2024 at 04:58:03PM +0100, Daniel P. Berrangé wrote:
> > > On Fri, Jul 26, 2024 at 04:47:40PM -0400, Peter Xu wrote:
> > > > On Fri, Jul 26, 2024 at 04:17:12PM +0100, Daniel P. Be
On Tue, Jul 30, 2024 at 09:26:20PM +0900, Akihiko Odaki wrote:
> On 2024/07/30 20:37, Michael S. Tsirkin wrote:
> > On Mon, Jul 15, 2024 at 02:19:06PM +0900, Akihiko Odaki wrote:
> > > Based-on: <20240714-rombar-v2-0-af1504ef5...@daynix.com>
> > > ("[PATCH v2 0/4] hw/pci: Convert rom_bar into OnOff
> diff --git a/hw/acpi/vmclock-abi.h b/hw/acpi/vmclock-abi.h
> new file mode 100644
> index 00..19cbf85efd
> --- /dev/null
> +++ b/hw/acpi/vmclock-abi.h
> @@ -0,0 +1,186 @@
> +/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR
> BSD-2-Clause) */
> +
> +/*
> + * This structur
Hello Chalapathi
On 7/30/24 19:23, Chalapathi V wrote:
Hello,
In patch v6 below issues detected during Coverity Scan were fixed.
- CID 1558831: Resource leaks (RESOURCE_LEAK)
Variable "rsp_payload" going out of scope leaks the storage it points to.
- CID 1558827:(OVERRUN)
Overrunnin
SPI controller device model supports a connection to a single SPI responder.
This provide access to SPI seeproms, TPM, flash device and an ADC controller.
All SPI function control is mapped into the SPI register space to enable full
control by firmware. In this commit SPI configuration component i
In this commit, create SPI controller on p10 chip and connect cs irq.
The QOM tree of pnv-spi and seeprom are.
/machine (powernv10-machine)
/chip[0] (power10_v2.0-pnv-chip)
/pib_spic[2] (pnv-spi)
/pnv-spi-bus.2 (SSI)
/xscom-spi[0] (memory-region)
/machine (powernv10-machine)
/
Add Microchip's 25CSM04 Serial EEPROM to m25p80. 25CSM04 provides 4 Mbits
of Serial EEPROM utilizing the Serial Peripheral Interface (SPI) compatible
bus. The device is organized as 524288 bytes of 8 bits each (512Kbyte) and
is optimized for use in consumer and industrial applications where reliab
In this commit Write a qtest pnv-spi-seeprom-test to check the
SPI transactions between spi controller and seeprom device.
Signed-off-by: Chalapathi V
Acked-by: Cédric Le Goater
Reviewed-by: Caleb Schlossin
---
tests/qtest/pnv-spi-seeprom-test.c | 110 +
tests/qtest
In this commit target specific dependency from include/hw/ppc/pnv_xscom.h
has been removed so that pnv_xscom.h can be included outside hw/ppc.
Signed-off-by: Chalapathi V
Reviewed-by: Cédric Le Goater
Reviewed-by: Caleb Schlossin
---
include/hw/ppc/pnv_xscom.h | 2 +-
1 file changed, 1 inserti
Hello,
In patch v6 below issues detected during Coverity Scan were fixed.
- CID 1558831: Resource leaks (RESOURCE_LEAK)
Variable "rsp_payload" going out of scope leaks the storage it points to.
- CID 1558827:(OVERRUN)
Overrunning array "s->seq_op" of 8 bytes at byte offset 16 using index
In this commit SPI shift engine and sequencer logic is implemented.
Shift engine performs serialization and de-serialization according to the
control by the sequencer and according to the setup defined in the
configuration registers. Sequencer implements the main control logic and
FSM to handle dat
From: Thomas Huth
Now that we converted many tests from the "check-avocado" test suite
to the "check-functional" test suite, we should make sure that these
also get tested in the CI.
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Thomas Huth
---
.gitlab-ci.d/buildtest-template.yml | 3 +-
.g
From: Thomas Huth
Provide a meson.build file for the upcoming python-based functional
tests, and add some wrapper glue targets to the tests/Makefile.include
file. We are going to use two "speed" modes for the functional tests:
The "quick" tests can be run at any time (i.e. also during "make check
The 'Asset' class is a simple module that declares a downloadable
asset that can be cached locally. Downloads are stored in the user's
home dir at ~/.cache/qemu/download, using a sha256 sum of the URL.
Signed-off-by: Daniel P. Berrangé
---
tests/functional/qemu_test/__init__.py | 1 +
tests/fun
From: Thomas Huth
Provide a "gzip_uncompress" function based on the standard "gzip" module
to avoid the usage of avocado.utils here.
Signed-off-by: Thomas Huth
---
tests/functional/meson.build | 4 ++
tests/functional/qemu_test/utils.py | 12
.../test_rx_gdbsim
From: Thomas Huth
These simple tests can be converted to stand-alone tests quite easily,
e.g. by just setting the machine to 'none' now manually or by adding
"-cpu" command line parameters, since we don't support the corresponding
avocado tags in the new python test framework.
Reviewed-by: Danie
From: Thomas Huth
The file is mostly a copy of the tests/avocado/avocado_qemu/__init__.py
file with some adjustments to get rid of the Avocado dependencies (i.e.
we also have to drop the LinuxSSHMixIn and LinuxTest for now).
The emulator binary and build directory are now passed via
environment
From: Thomas Huth
The avocado test defined test functions for both, riscv32 and riscv64.
Since we can run the whole file with multiple targets in the new
framework, we can now consolidate the functions so we have to only
define one function per machine now.
Reviewed-by: Alistair Francis
Signed-
From: Thomas Huth
Note: The original Avocado test seems currently to be broken, it hangs
when the guest is trying to install additional packages. So mark it as
broken for now until it gets fixed.
Signed-off-by: Thomas Huth
---
.../test_ppc64_hv.py} | 48
From: Thomas Huth
These tests use archive.lzma_uncompress() from the Avocado utils,
so provide a small helper function for this, based on the
standard lzma module from Python instead.
And while we're at it, replace the MD5 hashes in the topology test
with proper SHA256 hashes, since MD5 should n
From: Thomas Huth
Nothing thrilling in here, it's just a straight forward conversion.
Signed-off-by: Thomas Huth
---
tests/functional/meson.build | 1 +
.../test_virtio_gpu.py} | 64 +--
2 files changed, 30 insertions(+), 35 deletions(-)
From: Thomas Huth
Nothing thrilling in here, just straight forward conversions.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
MAINTAINERS | 8 +--
tests/functional/meson.build | 11
.../test_ppc64_powernv.py}
This series is an update to Thomas' v2:
https://lists.nongnu.org/archive/html/qemu-devel/2024-07/msg05805.html
wherein Thomas suggested someone could do the asset caching updates
while he is on vacation:
https://lists.nongnu.org/archive/html/qemu-devel/2024-07/msg06228.html
hence this posti
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