On 29/12/22 21:42, Peter Delevoryas wrote:
On Thu, Dec 29, 2022 at 04:23:17PM +0100, Philippe Mathieu-Daudé wrote:
Avoid confusing two different things:
- the WDT I/O region size ('iosize')
- at which offset the SoC map the WDT ('offset')
While it is often the same, we can map smaller region siz
On 29/12/22 21:46, Peter Delevoryas wrote:
On Thu, Dec 29, 2022 at 04:23:20PM +0100, Philippe Mathieu-Daudé wrote:
Since I don't have access to the datasheet, the relevant
values were found in:
https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
Signed-off-by: Ph
On Fri, Dec 30, 2022 at 3:17 AM Sriram Yagnaraman
wrote:
>
> > -Original Message-
> > From: Jason Wang
> > Sent: Friday, 23 December 2022 04:24
> > To: Sriram Yagnaraman
> > Cc: qemu-devel@nongnu.org; Dmitry Fleytman
> > ; Michael S . Tsirkin ;
> > Marcel Apfelbaum
> > Subject: Re: [PAT
From: Dongxue Zhang
Should be cpu->cfg.elen in range [8, 64].
Signed-off-by: Dongxue Zhang
Reviewed-by: LIU Zhiwei
Message-ID:
Reviewed-by: Frank Chang
Message-ID:
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/c
From: Dongxue Zhang
Should be cpu->cfg.elen in range [8, 64].
Signed-off-by: Dongxue Zhang
Reviewed-by: LIU Zhiwei
Reviewed-by: Frank Chang
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6fe176e483..5dc
>On Thu, Dec 29, 2022 at 12:34 AM ~elta wrote:
>>
>> From: Dongxue Zhang
>>
>> Should be cpu->cfg.elen in range [8, 64].
>>
>> Signed-off-by: Dongxue Zhang
>
>When sending a new version can you please add any previous reviewed tags.
>
>Alistair
>
Ok, i will try again, and add users as reviewed-
Prepare to replace a bunch of separate ifdefs with a
consistent way to describe the ABI of a function call.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg-internal.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/
From: Ilya Leoshkevich
Add a test that locklessly changes and exercises page protection bits
from various threads. This helps catch race conditions in the VMA
handling.
Acked-by: Alex Bennée
Signed-off-by: Ilya Leoshkevich
Message-Id: <20221223120252.513319-1-...@linux.ibm.com>
Signed-off-by:
Better to re-use the existing function for copying ops.
Acked-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/
Because we allow lockless lookups, we have to be careful
when it is freed. Use rcu to delay the free until safe.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git
For 32-bit hosts when TCG_TARGET_CALL_ALIGN_ARGS was set, use
TCG_CALL_ARG_EVEN. For 64-bit hosts, TCG_TARGET_CALL_ALIGN_ARGS
was silently ignored, so always use TCG_CALL_ARG_NORMAL.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 2 +-
The following changes since commit 222059a0fccf4af3be776fe35a5ea2d6a68f9a0b:
Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into
staging (2022-12-21 18:08:09 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-202
From: Philippe Mathieu-Daudé
We are going to modify this code, so fix its style first to avoid:
ERROR: spaces required around that '*' (ctx:VxV)
#281: FILE: tcg/s390x/tcg-target.c.inc:1224:
+uintptr_t mask = ~(0xull << i*16);
^
Revie
Move the error-generating fallback from tcg-op.c, and
replace "_link_error" with modern QEMU_ERROR markup.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h | 33 +
include/tcg/tcg.h| 12
tcg/tcg-intern
There are several instances where we need to be able to
allocate a pair of registers to related inputs/outputs.
Add 'p' and 'm' register constraints for this, in order to
be able to allocate the even/odd register first or second.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 2 +
tc
We copied all of the arguments in copy_op_nocheck.
We only need to replace the one argument that we change.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/accel/tcg/pl
The function pointer is immediately after the output and input
operands; no need to search.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 29 +++--
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/accel/t
While we initialize this value in cpu_common_reset, that
isn't called during startup, so set it as well in init.
This fixes -singlestep versus the very first TB.
Fixes: 04f5b647ed07 ("accel/tcg: Handle -singlestep in curr_cflags")
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
hw
From: Philippe Mathieu-Daudé
In order to have variable size allocated TCGOp, pass the number
of arguments we use (and would allocate) up to tcg_op_alloc().
This alters tcg_emit_op(), tcg_op_insert_before() and
tcg_op_insert_after() prototypes.
In tcg_op_alloc() ensure the number of arguments is
In addition, use tcg_enabled instead of !kvm_enabled.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
target/ppc/helper_regs.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/target/ppc/helper_reg
Remove whitespace at end of line, plus one place this also
highlights some missing braces.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 33 +
tcg/ppc/tcg-target.c.inc | 2 +-
2 files changed, 18 insertions(+
Instead of requiring a separate hash table lookup,
put a pointer to the CIF into TCGHelperInfo.
Signed-off-by: Richard Henderson
Message-Id: <2022074101.2069454-27-richard.hender...@linaro.org>
[PMD: Split from bigger patch]
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daud
Unused since commit 7b7d8b2d9a ("tcg/tci: Use ffi for calls").
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci.c| 1 -
tcg/tci/tcg-target.c.inc | 4
2 files changed, 5 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index bdfac83492..05a241
Allocate the first of a pair at the lower address, and the
second of a pair at the higher address. This will make it
easier to find the beginning of the larger memory block.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg-internal.h | 4 ++--
tcg/tcg.c
Change 32-bit tci TCG_TARGET_CALL_ARG_I32 to TCG_CALL_ARG_EVEN, to
force 32-bit values to be aligned to 64-bit. With a small reorg
to the argument processing loop, this neatly replaces an ifdef for
CONFIG_TCG_INTERPRETER.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
hw/mips/mips_int.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
index 2db5e10fe0..73437cd90f 100644
--- a/hw/mips/mips_int.c
+++ b/hw/mips/mips_int.
We now check the consistency of reg_to_temp[] with each update,
so the utility of checking consistency at the end of each
opcode is minimal. In addition, the form of this check is
quite expensive, consuming 10% of a checking-enabled build.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderso
Create a wrapper for locking/unlocking the iothread lock.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/qemu/main-loop.h | 29 +
1 file changed, 29 insertions(+)
diff --git a/include/qemu/main-loop.h b/include/qemu/main-loop.h
inde
From: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-Id: <2022074101.2069454-27-richard.hender...@linaro.org>
[PMD: Split from bigger patch]
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221122180804.938-3-phi...@linaro.org>
---
tcg/t
We will shortly have the possibility of more that two outputs,
though only for calls (for which preferences are moot). Avoid
direct references to op->output_pref[] when possible.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 5 +
tcg/tcg.c
For 64-bit hosts that had TCG_TARGET_EXTEND_ARGS, set
TCG_TARGET_CALL_ARG_I32 to TCG_CALL_ARG_EXTEND.
Otherwise, use TCG_CALL_ARG_NORMAL.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 1 +
tcg/arm/tcg-target.h | 1 +
tcg/i386/t
From: Philippe Mathieu-Daudé
In preparation of introducing paired registers,
massage a bit process_op_defs()'s switch case.
Signed-off-by: Richard Henderson
[PMD: Split from bigger patch, 1/3]
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221219220925.79218-2-phi...@linaro.org>
---
tcg
Add a helper function for computing the size of a type.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 16
tcg/tcg.c | 27 ---
2 files changed, 28 insertions(+), 15 deletions(-)
diff --git a/include/
Pre-compute the function call layout for each helper at startup.
Drop TCG_CALL_DUMMY_ARG, as we no longer need to leave gaps
in the op->args[] array. This allows several places to stop
checking for NULL TCGTemp, to which TCG_CALL_DUMMY_ARG mapped.
For tcg_gen_callN, loop over the arguments once.
There is only one use, and BLR is perhaps even more
self-documentary than CALLR.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aar
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
hw/ppc/ppc.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index dc86c1c7db..4e816c68c7 100644
--- a/hw/ppc/ppc.c
+++ b/hw/pp
The count is not itself an enumerator. Move it outside to
prevent the compiler from considering it with -Wswitch-enum.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/tcg/tc
As in page_get_flags, we need to try again with the mmap
lock held if we fail a page lookup.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 41 ++---
1 file changed, 34 insertions(+), 7 deletions(-)
diff --gi
When called from syscall(), we are not within a TB and pc == 0.
We can skip the check for invalidating the current TB.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/tb-maint.c | 78
1 file changed, 43 insertions(+
From: Philippe Mathieu-Daudé
In the unlikely case of invalid typecode mask, the function
will abort instead of returning a NULL pointer.
Signed-off-by: Richard Henderson
Message-Id: <2022074101.2069454-27-richard.hender...@linaro.org>
[PMD: Split from bigger patch]
Reviewed-by: Richard Hend
Like CONFIG_TCG, the enabled method of execution is a host property
not a guest property. This exposes the define to compile-once files.
Acked-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
meson.build | 4 +---
1 file changed, 1 insertion(+), 3 del
Record the location of a TCGTemp within a larger object.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 +
tcg/tcg.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index d207bc47be..afa18986b1
This eliminates an ifdef for TCI, and will be required for
expanding the call for TCGv_i128.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 12 ++--
tcg/aarch64/tcg-target.c.inc | 12 +---
tcg/arm/tcg-target.c.inc
Narrow the scope of the lock to the actual read/write,
moving the cpu_transation_failed call outside the lock.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 25 -
1 file changed, 8 insertions(+), 17 deletions(-)
diff --git
The first thing that temp_sync does is check mem_coherent,
so there's no need for the caller to do so.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 4f2e0
The assignment to mem_coherent should be done with any
modification, not simply with a newly allocated register.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 05d2b70ab7..371908b34b 100644
--- a/
The hppa host code has been removed since 2013; this
should have been deleted at the same time.
Fixes: 802b5081233a ("tcg-hppa: Remove tcg backend")
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 1 -
tcg/arm/tcg-target.h | 1 -
tcg/tcg
Create two new functions, set_temp_val_{reg,nonreg}.
Assert that the reg_to_temp mapping is correct before
any changes are made.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 159 +-
1 file changed, 85 insertions(+)
We have been allocating a worst case number of arguments
to support calls. Instead, allow the size to vary.
By default leave space for 4 args, to maximize reuse,
but allow calls to increase the number of args to 32.
Signed-off-by: Richard Henderson
[PMD: Split patch in two]
Signed-off-by: Philip
From: Mark Cave-Ayland
Convert tcg/README to rst and move it to docs/devel as a new "TCG Intermediate
Representation" page. There are a few minor changes to improve the aesthetic
of the final output which are as follows:
- Rename the title from "Tiny Code Generator - Fabrice Bellard" to "TCG
Replace goto allocate_in_reg with a boolean.
Remove o_preferred_regs which isn't used, except to copy.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 45 +
1 file changed, 21 insertions(+), 24 deletions(-)
diff -
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
target/ppc/excp_helper.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index add4d54ae7..287659c74d
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/cpu_helper.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 278d163803..241d06bab8 10064
Use the official extend/extract functions instead of routines
that will shortly be internal to tcg.
Cc: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 21 -
1 file changed, 4 insertions(+), 17 deletions(-
On Thu, Dec 29, 2022 at 12:34 AM ~elta wrote:
>
> From: Dongxue Zhang
>
> Should be cpu->cfg.elen in range [8, 64].
>
> Signed-off-by: Dongxue Zhang
When sending a new version can you please add any previous reviewed tags.
Alistair
> ---
> target/riscv/cpu.c | 2 +-
> 1 file changed, 1 inser
On Thu, Dec 29, 2022 at 04:23:23PM +0100, Philippe Mathieu-Daudé wrote:
> address_space_map() can fail:
>
> uart:~$ hash test
> sha256_test
> tv[0]:
> Segmentation fault: 11
> Thread 3 "qemu-system-arm" received signal SIGSEGV, Segmentation fault.
> gen_acc_mode_iov (req_len=0x718b
On Thu, Dec 29, 2022 at 04:23:24PM +0100, Philippe Mathieu-Daudé wrote:
> This SoC uses a Cortex-M4F. QEMU only implements a M4,
> which is good enough. Add a TODO note in case the M4F
> is added.
>
> Signed-off-by: Philippe Mathieu-Daudé
Oh, yeah good to have a note of this somewhere.
Reviewed
On Thu, Dec 29, 2022 at 04:23:25PM +0100, Philippe Mathieu-Daudé wrote:
> Add a very quick test that runs some commands in a Zephyr shell:
>
> $ tests/venv/bin/avocado --show=app,console run -t os:zephyr tests/avocado
> (2/2)
> tests/avocado/machine_aspeed.py:AST1030Machine.test_ast1030_zephy
On Thu, Dec 29, 2022 at 04:23:22PM +0100, Philippe Mathieu-Daudé wrote:
> Since I don't have access to the datasheet, the relevant
> values were found in:
> https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
>
> Before on Zephyr:
>
> uart:~$ crypto aes256_cbc_va
On Thu, Dec 29, 2022 at 04:23:21PM +0100, Philippe Mathieu-Daudé wrote:
> Some SRAM appears to be used by the Secure Boot unit and
> crypto accelerators. Name it 'secure sram'.
>
> Note, the SRAM base address was already present but unused
> (the 'SBC' index is used for the MMIO peripheral).
>
>
On Thu, Dec 29, 2022 at 04:23:20PM +0100, Philippe Mathieu-Daudé wrote:
> Since I don't have access to the datasheet, the relevant
> values were found in:
> https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/ar
:n Thu, Dec 29, 2022 at 04:23:19PM +0100, Philippe Mathieu-Daudé wrote:
> Based on booting Zephyr demo from [1] running QEMU with
> '-d unimp' and checking missing devices in [2].
>
> [1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07
> [2]
> https://github.com/AspeedTech-BMC/zep
On Thu, Dec 29, 2022 at 04:23:18PM +0100, Philippe Mathieu-Daudé wrote:
> IEC binary prefixes ease code review: the unit is explicit.
Oh, yeah, another good idea.
Reviewed-by: Peter Delevoryas
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/aspeed_ast10x0.c | 3 ++-
> hw/arm/aspeed_
On Thu, Dec 29, 2022 at 04:23:17PM +0100, Philippe Mathieu-Daudé wrote:
> Avoid confusing two different things:
> - the WDT I/O region size ('iosize')
> - at which offset the SoC map the WDT ('offset')
> While it is often the same, we can map smaller region sizes at
> larger offsets.
>
> Here we a
On Thu, Dec 29, 2022 at 04:23:16PM +0100, Philippe Mathieu-Daudé wrote:
> Trying to fix some bugs triggered running Zephyr.
Yay!
>
> Still 2 bugs:
>
> 1/
> uart:~$ sensor get SYSCLK
> [00:00:23.592,000] os: * USAGE FAULT *
> [00:00:23.593,000] os: Illegal use of the EPSR
> [00:00:23
> -Original Message-
> From: Jason Wang
> Sent: Friday, 23 December 2022 04:24
> To: Sriram Yagnaraman
> Cc: qemu-devel@nongnu.org; Dmitry Fleytman
> ; Michael S . Tsirkin ;
> Marcel Apfelbaum
> Subject: Re: [PATCH 0/5] hw/net/igb: emulated network device with SR-IOV
>
> On Thu, Dec 22,
Signed-off-by: Sriram Yagnaraman
---
hw/net/e1000_regs.h| 363 +
hw/net/e1000x_common.c | 13 ++
hw/net/e1000x_common.h | 29
3 files changed, 376 insertions(+), 29 deletions(-)
diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h
index 59e050
Also add return value for to send functions
Signed-off-by: Sriram Yagnaraman
---
hw/net/net_tx_pkt.c | 17 +++--
hw/net/net_tx_pkt.h | 8
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/hw/net/net_tx_pkt.c b/hw/net/net_tx_pkt.c
index 1cb1125d9f..f2e14008b6 1
> -Original Message-
> From: Alessandro Di Federico
> Sent: Wednesday, December 28, 2022 10:16 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Philippe Mathieu-Daudé
> ; Richard Henderson ;
> Alex Bennée
> Subject: [RFC] Reducing NEED_CPU_H usage
>
> Hello everyone, this is a pr
Only queue 0 is tested for TX/RX, and only PF is tested.
SRIOV/VF tests will come soon.
---
tests/qtest/igb-test.c | 222 +
tests/qtest/libqos/igb.c | 245 +
tests/qtest/libqos/igb.h | 51 +++
tests/qtest/libqos/m
Signed-off-by: Sriram Yagnaraman
---
hw/pci/pcie_sriov.c | 6 ++
include/hw/pci/pcie_sriov.h | 5 +
2 files changed, 11 insertions(+)
diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c
index 8e3faf1f59..88ba642a20 100644
--- a/hw/pci/pcie_sriov.c
+++ b/hw/pci/pcie_sriov.c
@@
A new attempt at adding support for Intel 82576 Gigabit Ethernet adapter
with SR-IOV support.
Start qemu with the following parameters.
qemu-system-x86_64 -enable-kvm -M q35 \
...
-device pcie-root-port,slot=3,id=pcie_port.3 \
-netdev tap,id=net3,script=no,downscript=/tmp/rmtap,ifname=
> -Original Message-
> From: Akihiko Odaki
> Sent: Thursday, 29 December 2022 03:43
> To: Jason Wang ; Sriram Yagnaraman
>
> Cc: qemu-devel@nongnu.org; Dmitry Fleytman
> ; Michael S . Tsirkin ;
> Marcel Apfelbaum ; Yan Vugenfirer
>
> Subject: Re: [PATCH 0/5] hw/net/igb: emulated network
Signed-off-by: Sriram Yagnaraman
---
hw/i386/Kconfig| 1 +
hw/net/Kconfig | 5 +
hw/net/igb_core.c | 4 +---
hw/net/meson.build | 2 ++
4 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index d22ac4a4b9..97a0b08842 100644
--- a/hw/i386/K
All callers are using kernel_filename as machine->kernel_filename.
This will also simplify the changes in riscv_load_kernel() that we're
going to do next.
Cc: Palmer Dabbelt
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
---
hw/riscv/boot.c
The only remaining caller is riscv_load_kernel_and_initrd() which
belongs to the same file.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
---
hw/riscv/boot.c | 80 -
include/hw/riscv/boot.h | 1
This test is used to do a quick sanity check to ensure that we're able
to run the existing QEMU FW image.
'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
RISCV32_BIOS_BIN firmware with minimal options.
The r
This will make the code more in line with what the other boards are
doing. We'll also avoid an extra check to machine->kernel_filename since
we already checked that before executing riscv_load_kernel().
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alist
The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
the same steps when '-kernel' is used:
- execute load_kernel()
- load init_rd()
- write kernel_cmdline in the fdt
Let's fold everything inside riscv_load_kernel() to avoid code
repetition. Every other board that uses riscv_lo
The MachineState object provides a 'fdt' pointer that is already being
used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
command.
Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt
instead.
Cc: Palmer Dabbelt
Signed-off-by: Daniel Henrique Barboza
Reviewed
'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be
retrieved by the MachineState object for all callers.
Cc: Palmer Dabbelt
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
---
hw/riscv/boot.c| 6 --
hw/riscv/mi
The MachineState object provides a 'fdt' pointer that is already being
used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
command.
Remove the 'fdt' pointer from SpikeState and use MachineState::fdt
instead.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-
riscv_load_kernel() and riscv_load_initrd() works under the assumption
that 'kernel_filename' and 'filename' are not NULL.
This is currently the case since all callers of both functions are
checking for NULL before calling them. Put an assert in both to make
sure that a NULL value for both cases w
The sifive_u, spike and virt machines are writing the 'bootargs' FDT
node during their respective create_fdt().
Given that bootargs is written only when '-append' is used, and this
option is only allowed with the '-kernel' option, which in turn is
already being check before executing riscv_load_ke
Hi,
This new version is still rebased on top of [1]:
"[PATCH 00/12] hw/riscv: Improve Spike HTIF emulation fidelity"
from Bin Meng.
In this version there's a new patch, patch 4, where we added a
g_assert() guard in both riscv_load_kernel() and riscv_load_initrd(), as
proposed by Alex in the v3
riscv_load_initrd() returns the initrd end addr while also writing a
'start' var to mark the addr start. These informations are being used
just to write the initrd FDT node. Every existing caller of
riscv_load_initrd() is writing the FDT in the same manner.
We can simplify things by writing the FD
From: Saleem Abdulrasool
Setting the rounding mode via the `gen_set_rm` call would alter the
state of the disassembler, resetting the `TransOp` in the assembler
context. When we subsequently set the rounding mode to the desired
value, we would trigger an assertion in `decode_save_opc`. Instead
On 29/12/22 18:37, Saleem Abdulrasool wrote:
From: Saleem Abdulrasool
Setting the rounding mode via the `gen_set_rm` call would alter the
state of the disassembler, resetting the `TransOp` in the assembler
context. When we subsequently set the rounding mode to the desired
value, we would trigg
From: Saleem Abdulrasool
Setting the rounding mode via the `gen_set_rm` call would alter the
state of the disassembler, resetting the `TransOp` in the assembler
context. When we subsequently set the rounding mode to the desired
value, we would trigger an assertion in `decode_save_opc`. Instead
Yes, the formatting is correct in patchew.
I'll include these in my next PR.
Thanks,
Taylor
> -Original Message-
> From: Mukilan Thiyagarajan (QUIC)
> Sent: Thursday, December 29, 2022 3:28 AM
> To: Taylor Simpson ; Mukilan Thiyagarajan (QUIC)
> ; qemu-devel@nongnu.org;
> laur...@vivie
Add a very quick test that runs some commands in a Zephyr shell:
$ tests/venv/bin/avocado --show=app,console run -t os:zephyr tests/avocado
(2/2)
tests/avocado/machine_aspeed.py:AST1030Machine.test_ast1030_zephyros_1_07:
console: *** Booting Zephyr OS build v00.01.07 ***
console: ast1030
Since I don't have access to the datasheet, the relevant
values were found in:
https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
Before on Zephyr:
uart:~$ crypto aes256_cbc_vault
aes256_cbc vault key 1
[00:00:06.699,000] hace_global: aspeed_crypto_session_
Based on booting Zephyr demo from [1] running QEMU with
'-d unimp' and checking missing devices in [2].
[1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07
[2]
https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
Signed-off-by: Philippe Mathieu-Daud
Since I don't have access to the datasheet, the relevant
values were found in:
https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/aspeed_ast10x0.c | 16
1 file changed, 16 insertions(+)
diff --git
Avoid confusing two different things:
- the WDT I/O region size ('iosize')
- at which offset the SoC map the WDT ('offset')
While it is often the same, we can map smaller region sizes at
larger offsets.
Here we are interested in the I/O region size. Rename as 'iosize'
and map the whole range, not
Some SRAM appears to be used by the Secure Boot unit and
crypto accelerators. Name it 'secure sram'.
Note, the SRAM base address was already present but unused
(the 'SBC' index is used for the MMIO peripheral).
Interestingly using CFLAGS=-Winitializer-overrides reports:
../hw/arm/aspeed_ast10x
This SoC uses a Cortex-M4F. QEMU only implements a M4,
which is good enough. Add a TODO note in case the M4F
is added.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/aspeed_ast10x0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast
address_space_map() can fail:
uart:~$ hash test
sha256_test
tv[0]:
Segmentation fault: 11
Thread 3 "qemu-system-arm" received signal SIGSEGV, Segmentation fault.
gen_acc_mode_iov (req_len=0x718b7778, id=,
iov=0x718b7780, s=0x56ce0bd0)
at ../hw/misc/aspeed_hace.c:171
Trying to fix some bugs triggered running Zephyr.
Still 2 bugs:
1/
uart:~$ sensor get SYSCLK
[00:00:23.592,000] os: * USAGE FAULT *
[00:00:23.593,000] os: Illegal use of the EPSR
[00:00:23.593,000] os: r0/a1: 0x00033448 r1/a2: 0x r2/a3:
0x00047f50
[00:00:23.593,000] os
IEC binary prefixes ease code review: the unit is explicit.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/aspeed_ast10x0.c | 3 ++-
hw/arm/aspeed_ast2600.c | 3 ++-
hw/arm/aspeed_soc.c | 4 ++--
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/ar
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