Hi,
This new version is still rebased on top of [1]:
"[PATCH 00/12] hw/riscv: Improve Spike HTIF emulation fidelity"
from Bin Meng.
In this version there's a new patch, patch 4, where we added a
g_assert() guard in both riscv_load_kernel() and riscv_load_initrd(), as
proposed by Alex in the v3 review.
There were also some aesthetic changes were made in patch 1 w.r.t the
order of the tests in the avocado file and fixing 'opensbi' and
'Opensbi' instances to 'OpenSBI'.
* Patch without reviews: 3
Changes from v3:
- patch 1:
- fixed more instances of 'opensbi' and 'Opensbi' to 'OpenSBI'
- changed tests order
- patch 4 (new):
- added a g_assert(filename) guard in riscv_load_initrd() and
riscv_load_kernel()
v3 link: https://mail.gnu.org/archive/html/qemu-devel/2022-12/msg04491.html
Changes from v2:
- patch 1:
- reduced code repetition with a boot_opensbi() helper
- renamed 'opensbi' to 'OpenSBI' in the file header
- patch 9:
- renamed riscv_load_kernel() to riscv_load_kernel_and_initrd()
v2 link: https://mail.gnu.org/archive/html/qemu-devel/2022-12/msg04466.html
Changes from v1:
- patches were rebased with [1]
- patches 13-15: removed
* will be re-sent in a follow-up series
- patches 4-5: removed since they're picked by Bin in [1]
- patch 1:
- added a 'skip' riscv32 spike test
v1 link: https://mail.gnu.org/archive/html/qemu-devel/2022-12/msg03860.html
Based-on: <20221227064812.1903326-1-bm...@tinylab.org>
Cc: Alistair Francis <alistair.fran...@wdc.com>
Cc: Bin Meng <bin.m...@windriver.com>
[1] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159
Daniel Henrique Barboza (11):
tests/avocado: add RISC-V OpenSBI boot test
hw/riscv/spike: use 'fdt' from MachineState
hw/riscv/sifive_u: use 'fdt' from MachineState
hw/riscv/boot.c: exit early if filename is NULL in
load_(kernel|initrd)
hw/riscv/spike.c: load initrd right after riscv_load_kernel()
hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()
hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()
hw/riscv/boot.c: use MachineState in riscv_load_initrd()
hw/riscv/boot.c: use MachineState in riscv_load_kernel()
hw/riscv/boot.c: introduce riscv_load_kernel_and_initrd()
hw/riscv/boot.c: make riscv_load_initrd() static
hw/riscv/boot.c | 92 ++++++++++++++++++++++------------
hw/riscv/microchip_pfsoc.c | 20 +-------
hw/riscv/opentitan.c | 3 +-
hw/riscv/sifive_e.c | 4 +-
hw/riscv/sifive_u.c | 32 +++---------
hw/riscv/spike.c | 38 ++++----------
hw/riscv/virt.c | 21 +-------
include/hw/riscv/boot.h | 8 ++-
include/hw/riscv/sifive_u.h | 3 --
include/hw/riscv/spike.h | 2 -
tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++
11 files changed, 151 insertions(+), 137 deletions(-)
create mode 100644 tests/avocado/riscv_opensbi.py
--
2.38.1
